drivers: cache: add NXP LMEM cache driver

Add LMEM cache driver implementing instruction cache ops.
Wire driver into cache Kconfig menu and CMake build.
Enables I-cache control on SoCs with NXP LMEM controller.

Signed-off-by: Holt Sun <[email protected]>

Author: Holt-Sun

drivers/cache/CMakeLists.txt

@@ -12,6 +12,7 @@ zephyr_library_sources_ifdef(CONFIG_CACHE_ANDES cache_andes.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_ASPEED cache_aspeed.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_BFLB_L1C cache_bflb_l1c.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_NRF_CACHE cache_nrf.c)
+zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_LMEM_CACHE cache_nxp_lmem_cache.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_NXP_XCACHE cache_nxp_xcache.c)
 zephyr_library_sources_ifdef(CONFIG_CACHE_STM32 cache_stm32.c)
 # zephyr-keep-sorted-stop

drivers/cache/Kconfig

@@ -23,6 +23,7 @@ source "drivers/cache/Kconfig.andes"
 source "drivers/cache/Kconfig.aspeed"
 source "drivers/cache/Kconfig.bflb"
 source "drivers/cache/Kconfig.nrf"
+source "drivers/cache/Kconfig.nxp_lmem_cache"
 source "drivers/cache/Kconfig.nxp_xcache"
 source "drivers/cache/Kconfig.stm32"
 # zephyr-keep-sorted-stop

drivers/cache/Kconfig.nxp_lmem_cache

@@ -0,0 +1,10 @@
+# Copyright 2025 NXP
+# SPDX-License-Identifier: Apache-2.0
+
+config CACHE_NXP_LMEM_CACHE
+	bool "NXP LMEM cache driver"
+	default y
+	select CACHE_HAS_DRIVER
+	depends on HAS_MCUX_LMEM_CACHE
+	help
+	  This option enables the LMEM cache driver for NXP SOCs.

drivers/cache/cache_nxp_lmem_cache.c

@@ -0,0 +1,62 @@
+/*
+ * Copyright 2025 NXP
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/kernel.h>
+#include <zephyr/drivers/cache.h>
+#include <zephyr/logging/log.h>
+#include <fsl_cache.h>
+
+void cache_instr_enable(void)
+{
+	L1CACHE_EnableCodeCache();
+}
+
+void cache_instr_disable(void)
+{
+	L1CACHE_DisableCodeCache();
+}
+
+int cache_instr_flush_all(void)
+{
+	L1CACHE_CleanCodeCache();
+
+	return 0;
+}
+
+int cache_instr_invd_all(void)
+{
+	L1CACHE_InvalidateCodeCache();
+
+	return 0;
+}
+
+int cache_instr_flush_and_invd_all(void)
+{
+	L1CACHE_CleanInvalidateCodeCache();
+
+	return 0;
+}
+
+int cache_instr_flush_range(void *addr, size_t size)
+{
+	L1CACHE_CleanCodeCacheByRange((uint32_t)addr, (uint32_t)size);
+
+	return 0;
+}
+
+int cache_instr_invd_range(void *addr, size_t size)
+{
+	L1CACHE_InvalidateCodeCacheByRange((uint32_t)addr, (uint32_t)size);
+
+	return 0;
+}
+
+int cache_instr_flush_and_invd_range(void *addr, size_t size)
+{
+	L1CACHE_CleanInvalidateCodeCacheByRange((uint32_t)addr, (uint32_t)size);
+
+	return 0;
+}