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7 | 7 | #include <zephyr/devicetree.h> |
8 | 8 | #include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h> |
9 | 9 |
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10 | | -#define REGION_HYPERRAM_BASE_ADDRESS 0x04000000 |
11 | | -#define REGION_HYPERRAM_SIZE 0x04000000 |
12 | | -#define REGION_DTCM_BASE_ADDRESS 0x20000000 |
| 10 | +#define REGION_FLEXSPI2_BASE_ADDRESS 0x14000000 |
| 11 | +#define REGION_FLEXSPI2_SIZE 0x04000000 |
| 12 | +#define REGION_DTCM_BASE_ADDRESS 0x30000000 |
13 | 13 | #define REGION_DTCM_SIZE 0x00020000 |
14 | | -#define REGION_FLEXSPI_BASE_ADDRESS 0x28000000 |
| 14 | +#define REGION_FLEXSPI_BASE_ADDRESS 0x38000000 |
15 | 15 | #define REGION_FLEXSPI_SIZE 0x08000000 |
16 | | -#define REGION_PERIPHERAL_BASE_ADDRESS 0x40000000 |
| 16 | +#define REGION_PERIPHERAL_BASE_ADDRESS 0x50000000 |
17 | 17 | #define REGION_PERIPHERAL_SIZE 0x40000000 |
18 | 18 |
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19 | 19 | static const struct arm_mpu_region mpu_regions[] = { |
20 | | - MPU_REGION_ENTRY("HYPERRAM", REGION_HYPERRAM_BASE_ADDRESS, |
21 | | - REGION_RAM_ATTR(REGION_HYPERRAM_BASE_ADDRESS, REGION_HYPERRAM_SIZE)), |
| 20 | + MPU_REGION_ENTRY("FLEXSPI2", REGION_FLEXSPI2_BASE_ADDRESS, |
| 21 | + REGION_RAM_ATTR(REGION_FLEXSPI2_BASE_ADDRESS, REGION_FLEXSPI2_SIZE)), |
22 | 22 | MPU_REGION_ENTRY("FLEXSPI", REGION_FLEXSPI_BASE_ADDRESS, |
23 | 23 | REGION_FLASH_ATTR(REGION_FLEXSPI_BASE_ADDRESS, REGION_FLEXSPI_SIZE)), |
24 | 24 | MPU_REGION_ENTRY("DTCM", REGION_DTCM_BASE_ADDRESS, |
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