@@ -1071,11 +1071,11 @@ static int eth_initialize(const struct device *dev)
10711071#endif
10721072 heth -> Init .MACAddr = dev_data -> mac_addr ;
10731073
1074- #if defined(CONFIG_SOC_SERIES_STM32H7X )
1074+ #if defined(CONFIG_SOC_SERIES_STM32H7X ) || defined( CONFIG_ETH_STM32_HAL_API_V2 )
10751075 heth -> Init .TxDesc = dma_tx_desc_tab ;
10761076 heth -> Init .RxDesc = dma_rx_desc_tab ;
10771077 heth -> Init .RxBuffLen = ETH_STM32_RX_BUF_SIZE ;
1078- #endif /* CONFIG_SOC_SERIES_STM32H7X */
1078+ #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_ETH_STM32_HAL_API_V2 */
10791079
10801080 hal_ret = HAL_ETH_Init (heth );
10811081 if (hal_ret == HAL_TIMEOUT ) {
@@ -1099,23 +1099,23 @@ static int eth_initialize(const struct device *dev)
10991099#endif /* CONFIG_SOC_SERIES_STM32H7X */
11001100#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
11011101
1102- #if defined(CONFIG_SOC_SERIES_STM32H7X )
1102+ #if defined(CONFIG_SOC_SERIES_STM32H7X ) || defined( CONFIG_ETH_STM32_HAL_API_V2 )
11031103 /* Tx config init: */
11041104 memset (& tx_config , 0 , sizeof (ETH_TxPacketConfig ));
11051105 tx_config .Attributes = ETH_TX_PACKETS_FEATURES_CSUM |
11061106 ETH_TX_PACKETS_FEATURES_CRCPAD ;
11071107 tx_config .ChecksumCtrl = ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ;
11081108 tx_config .CRCPadCtrl = ETH_CRC_PAD_INSERT ;
1109- #endif /* CONFIG_SOC_SERIES_STM32H7X */
1109+ #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_ETH_STM32_HAL_API_V2 */
11101110
11111111 dev_data -> link_up = false;
11121112
11131113 /* Initialize semaphores */
11141114 k_mutex_init (& dev_data -> tx_mutex );
11151115 k_sem_init (& dev_data -> rx_int_sem , 0 , K_SEM_MAX_LIMIT );
1116- #ifdef CONFIG_SOC_SERIES_STM32H7X
1116+ #if defined( CONFIG_SOC_SERIES_STM32H7X ) || defined( CONFIG_ETH_STM32_HAL_API_V2 )
11171117 k_sem_init (& dev_data -> tx_int_sem , 0 , K_SEM_MAX_LIMIT );
1118- #endif /* CONFIG_SOC_SERIES_STM32H7X */
1118+ #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_ETH_STM32_HAL_API_V2 */
11191119
11201120 /* Start interruption-poll thread */
11211121 k_thread_create (& dev_data -> rx_thread , dev_data -> rx_thread_stack ,
@@ -1126,7 +1126,15 @@ static int eth_initialize(const struct device *dev)
11261126
11271127 k_thread_name_set (& dev_data -> rx_thread , "stm_eth" );
11281128
1129- #if defined(CONFIG_SOC_SERIES_STM32H7X )
1129+ #if defined(CONFIG_ETH_STM32_HAL_API_V2 )
1130+
1131+ /* prepare tx buffer header */
1132+ for (uint16_t i = 0 ; i < ETH_TXBUFNB ; ++ i ) {
1133+ dma_tx_buffer_header [i ].tx_buff .buffer = dma_tx_buffer [i ];
1134+ }
1135+
1136+ hal_ret = HAL_ETH_Start_IT (heth );
1137+ #elif defined(CONFIG_SOC_SERIES_STM32H7X )
11301138 for (uint32_t i = 0 ; i < ETH_RX_DESC_CNT ; i ++ ) {
11311139 hal_ret = HAL_ETH_DescAssignMemory (heth , i , dma_rx_buffer [i ],
11321140 NULL );
@@ -1145,15 +1153,15 @@ static int eth_initialize(const struct device *dev)
11451153 & dma_rx_buffer [0 ][0 ], ETH_RXBUFNB );
11461154
11471155 hal_ret = HAL_ETH_Start (heth );
1148- #endif /* CONFIG_SOC_SERIES_STM32H7X */
1156+ #endif /* CONFIG_ETH_STM32_HAL_API_V2 */
11491157
11501158 if (hal_ret != HAL_OK ) {
11511159 LOG_ERR ("HAL_ETH_Start{_IT} failed" );
11521160 }
11531161
11541162 disable_mcast_filter (heth );
11551163
1156- #if defined(CONFIG_SOC_SERIES_STM32H7X )
1164+ #if defined(CONFIG_SOC_SERIES_STM32H7X ) || defined( CONFIG_ETH_STM32_HAL_API_V2 )
11571165 /* Adjust MDC clock range depending on HCLK frequency: */
11581166 HAL_ETH_SetMDIOClockRange (heth );
11591167
@@ -1165,7 +1173,7 @@ static int eth_initialize(const struct device *dev)
11651173 mac_config .DuplexMode = ETH_FULLDUPLEX_MODE ;
11661174 mac_config .Speed = ETH_SPEED_100M ;
11671175 HAL_ETH_SetMACConfig (heth , & mac_config );
1168- #endif /* CONFIG_SOC_SERIES_STM32H7X */
1176+ #endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_ETH_STM32_HAL_API_V2 */
11691177
11701178 LOG_DBG ("MAC %02x:%02x:%02x:%02x:%02x:%02x" ,
11711179 dev_data -> mac_addr [0 ], dev_data -> mac_addr [1 ],
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