soc: xtensa: Add mimxrt685s/hifi4

Add definitions, linker file and init code for mimxrt685s/hifi4 (i.MX
RT685's HiFi 4 DSP).

Signed-off-by: Vit Stanicek <[email protected]>

Author: VitekST

soc/nxp/imxrt/imxrt6xx/CMakeLists.txt

@@ -7,3 +7,7 @@
 if(CONFIG_SOC_MIMXRT685S_CM33)
   add_subdirectory(cm33)
 endif()
+
+if(CONFIG_SOC_MIMXRT685S_HIFI4)
+  add_subdirectory(hifi4)
+endif()

soc/nxp/imxrt/imxrt6xx/Kconfig

@@ -32,10 +32,23 @@ config SOC_MIMXRT685S_CM33
 	select HAS_MCUX_CTIMER
 	select SOC_EARLY_INIT_HOOK
 
+config SOC_MIMXRT685S_HIFI4
+	select XTENSA
+	select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
+	select XTENSA_RESET_VECTOR
+	select XTENSA_USE_CORE_CRT1
+	select CLOCK_CONTROL
+	select HAS_MCUX
+	select HAS_MCUX_SYSCON
+	select SOC_EARLY_INIT_HOOK
+
 if SOC_SERIES_IMXRT6XX
 
 config MCUX_CORE_SUFFIX
 	default "_cm33" if SOC_MIMXRT685S_CM33
+	default "_dsp" if SOC_MIMXRT685S_HIFI4
+
+if SOC_MIMXRT685S_CM33
 
 config INIT_SYS_PLL
 	bool "Initialize SYS PLL"
@@ -62,4 +75,45 @@ config IMXRT6XX_CODE_CACHE
 	  Enable code cache for FlexSPI region at boot. If this Kconfig is
 	  cleared, the CACHE64 controller will be disabled during SOC init
 
-endif
+endif # SOC_MIMXRT685S_CM33
+
+if SOC_MIMXRT685S_HIFI4
+
+DT_ADSP_RESET_MEM := $(dt_nodelabel_path,adsp_reset)
+DT_ADSP_DATA_MEM := $(dt_nodelabel_path,adsp_data)
+DT_ADSP_TEXT_MEM := $(dt_nodelabel_path,adsp_text)
+
+config RT685_ADSP_STACK_SIZE
+	hex "Boot time stack size"
+	default 0x1000
+	help
+	  Stack space is reserved at the end of the RT685_ADSP_DATA_MEM
+	  region, starting at RT685_ADSP_DATA_MEM_ADDR - RT685_ADSP_STACK_SIZE
+
+config RT685_ADSP_RESET_MEM_ADDR
+	hex
+	default $(dt_node_reg_addr_hex,$(DT_ADSP_RESET_MEM))
+
+config RT685_ADSP_RESET_MEM_SIZE
+	hex
+	default $(dt_node_reg_size_hex,$(DT_ADSP_RESET_MEM))
+
+config RT685_ADSP_DATA_MEM_ADDR
+	hex
+	default $(dt_node_reg_addr_hex,$(DT_ADSP_DATA_MEM))
+
+config RT685_ADSP_DATA_MEM_SIZE
+	hex
+	default $(dt_node_reg_size_hex,$(DT_ADSP_DATA_MEM))
+
+config RT685_ADSP_TEXT_MEM_ADDR
+	hex
+	default $(dt_node_reg_addr_hex,$(DT_ADSP_TEXT_MEM))
+
+config RT685_ADSP_TEXT_MEM_SIZE
+	hex
+	default $(dt_node_reg_size_hex,$(DT_ADSP_TEXT_MEM))
+
+endif # SOC_MIMXRT685S_HIFI4
+
+endif # SOC_SERIES_IMXRT6XX

soc/nxp/imxrt/imxrt6xx/Kconfig.defconfig

@@ -65,3 +65,13 @@ config SYS_CLOCK_HW_CYCLES_PER_SEC
 endif # CORTEX_M_SYSTICK
 
 endif # SOC_MIMXRT685S_CM33
+
+if SOC_MIMXRT685S_HIFI4
+
+config SYS_CLOCK_HW_CYCLES_PER_SEC
+	default 198000000
+
+config MCUX_CORE_SUFFIX
+	default "_dsp"
+
+endif # SOC_MIMXRT685S_HIFI4

soc/nxp/imxrt/imxrt6xx/Kconfig.soc

@@ -12,26 +12,34 @@ config SOC_MIMXRT685S
 	bool
 	select SOC_SERIES_IMXRT6XX
 
+config SOC
+	default "mimxrt685s" if SOC_MIMXRT685S
+
 config SOC_MIMXRT685S_CM33
 	bool
 	select SOC_MIMXRT685S
 
-config SOC
-	default "mimxrt685s" if SOC_MIMXRT685S_CM33
+config SOC_MIMXRT685S_HIFI4
+	bool
+	select SOC_MIMXRT685S
 
 config SOC_PART_NUMBER_MIMXRT685SFVKB
+	select SOC_MIMXRT685S
 	bool
-	select SOC_MIMXRT685S_CM33
 
 config SOC_PART_NUMBER_MIMXRT685SFFOB
+	select SOC_MIMXRT685S
 	bool
-	select SOC_MIMXRT685S_CM33
 
 config SOC_PART_NUMBER_MIMXRT685SFAWBR
+	select SOC_MIMXRT685S
 	bool
-	select SOC_MIMXRT685S_CM33
 
 config SOC_PART_NUMBER
 	default "MIMXRT685SFVKB" if SOC_PART_NUMBER_MIMXRT685SFVKB
 	default "MIMXRT685SFFOB" if SOC_PART_NUMBER_MIMXRT685SFFOB
 	default "MIMXRT685SFAWBR" if SOC_PART_NUMBER_MIMXRT685SFAWBR
+
+config SOC_TOOLCHAIN_NAME
+	string
+	default "nxp_rt600_adsp" if SOC_MIMXRT685S_HIFI4

soc/nxp/imxrt/imxrt6xx/hifi4/CMakeLists.txt

@@ -0,0 +1,16 @@
+#
+# Copyright 2025 NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+zephyr_include_directories(.)
+zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
+zephyr_sources(soc.c)
+
+zephyr_library_include_directories(
+  ${ZEPHYR_BASE}/kernel/include
+  ${ZEPHYR_BASE}/arch/${ARCH}/include
+)
+
+set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")