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drivers: pinctrl: add CC13XX/CC26XX pinctrl driver
Add pinctrl driver for CC13XX/CC26XX family of SoCs to facilitate transition from pinmux to pinctrl. `IOCPortConfigureSet()` from TI hal driverlib used to implement the generic pinctrl driver. Signed-off-by: Vaishnav Achath <[email protected]>
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‎drivers/pinctrl/CMakeLists.txt‎

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@@ -17,3 +17,4 @@ zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCHP_XEC pinctrl_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_MCUX_RT pinctrl_mcux_rt.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_SIFIVE pinctrl_sifive.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_NXP_IOCON pinctrl_lpc_iocon.c)
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zephyr_library_sources_ifdef(CONFIG_PINCTRL_CC13XX_CC26XX pinctrl_cc13xx_cc26xx.c)

‎drivers/pinctrl/Kconfig‎

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@@ -42,5 +42,6 @@ source "drivers/pinctrl/Kconfig.xec"
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source "drivers/pinctrl/Kconfig.mcux"
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source "drivers/pinctrl/Kconfig.sifive"
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source "drivers/pinctrl/Kconfig.lpc_iocon"
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source "drivers/pinctrl/Kconfig.cc13xx_cc26xx"
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endif # PINCTRL

‎drivers/pinctrl/Kconfig.cc13xx_cc26xx‎

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# Copyright (c) 2022 Vaishnav Achath
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# SPDX-License-Identifier: Apache-2.0
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DT_COMPAT_CC13XX_CC26XX_PINCTRL := ti,cc13xx-cc26xx-pinctrl
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config PINCTRL_CC13XX_CC26XX
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bool "TI SimpleLink CC13xx / CC26xx pinctrl driver"
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depends on SOC_SERIES_CC13X2_CC26X2
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default $(dt_compat_enabled,$(DT_COMPAT_CC13XX_CC26XX_PINCTRL))
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help
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Enable the TI SimpleLink CC13xx / CC26xx pinctrl driver

‎drivers/pinctrl/pinctrl_cc13xx_cc26xx.c‎

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/*
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* Copyright (c) 2022 Vaishnav Achath
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT ti_cc13xx_cc26xx_pinctrl
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#include <drivers/pinctrl.h>
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#include <driverlib/ioc.h>
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static int pinctrl_c13xx_cc26xx_set(uint32_t pin, uint32_t func, uint32_t mode)
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{
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if (pin >= NUM_IO_MAX || func >= NUM_IO_PORTS) {
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return -EINVAL;
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}
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IOCPortConfigureSet(pin, func, mode);
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return 0;
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}
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int pinctrl_configure_pins(const pinctrl_soc_pin_t *pins, uint8_t pin_cnt, uintptr_t reg)
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{
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ARG_UNUSED(reg);
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for (uint8_t i = 0U; i < pin_cnt; i++) {
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pinctrl_c13xx_cc26xx_set(pins[i].pin, pins[i].iofunc, pins[i].iomode);
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}
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return 0;
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}

‎dts/bindings/pinctrl/ti,cc13xx-cc26xx-pinctrl.yaml‎

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# Copyright (c) 2022 Vaishnav Achath
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# SPDX-License-Identifier: Apache-2.0
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description: |
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TI SimpleLink CC13xx / CC26xx pinctrl node.
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Device pin configuration should be placed in the child nodes of this node.
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Populate the 'pinmux' field with a pair consisting of a pin number and its IO
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functions.
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The node has the 'pinctrl' node label set in your SoC's devicetree,
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so you can modify it like this:
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&pinctrl {
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/* your modifications go here */
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};
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All device pin configurations should be placed in child nodes of the
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'pinctrl' node, as in the i2c0 example shown at the end.
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Here is a list of
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supported standard pin properties:
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- bias-disable: Disable pull-up/down.
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- bias-pull-down: Enable pull-down resistor.
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- bias-pull-up: Enable pull-up resistor.
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- drive-open-drain: Output driver is open-drain.
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- drive-open-drain: Output driver is open-source.
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- input-enable: enable input.
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- input-schmitt-enable: enable input schmitt circuit.
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An example for CC13XX family, include the chip level pinctrl
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DTSI file in the board level DTS:
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#include <dt-bindings/pinctrl/cc13xx_cc26xx-pinctrl.h>
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We want to configure the I2C pins to open drain, with pullup enabled
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and input enabled.
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To change a pin's pinctrl default properties add a reference to the
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pin in the board's DTS file and set the properties.
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&i2c0 {
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pinctrl-0 = <&i2c0_scl_default &i2c0_sda_default>;
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pinctrl-1 = <&i2c0_scl_sleep &i2c0_sda_sleep>;
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pinctrl-names = "default", "sleep";
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}
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The i2c0_scl_default corresponds to the following in the board dts file:
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&pinctrl {
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i2c0_scl_default: i2c0_scl_default {
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pinmux = <4 IOC_PORT_MCU_I2C_MSSCL>;
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bias-pull-up;
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drive-open-drain;
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input-enable;
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};
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};
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compatible: "ti,cc13xx-cc26xx-pinctrl"
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include:
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- name: base.yaml
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- name: pincfg-node.yaml
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child-binding:
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property-allowlist:
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- bias-disable
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- bias-pull-down
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- bias-pull-up
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- drive-open-drain
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- drive-open-source
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- input-enable
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- input-schmitt-enable
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properties:
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reg:
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required: true
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child-binding:
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description: |
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This binding gives a base representation of the CC13XX/CC26XX
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pins configuration.
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properties:
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pinmux:
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required: true
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type: array
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description: |
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CC13XX/CC26XX pin's configuration (IO pin, IO function).

‎include/zephyr/dt-bindings/pinctrl/cc13xx_cc26xx-pinctrl.h‎

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/*
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* Copyright (c) 2015 - 2017, Texas Instruments Incorporated
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef CC13XX_CC26XX_PINCTRL_COMMON_H_
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#define CC13XX_CC26XX_PINCTRL_COMMON_H_
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/* Adapted from hal/ti/simplelink/source/ti/devices/cc13x2_cc26x2/driverlib/ioc.h */
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/* IOC Peripheral Port Mapping */
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#define IOC_PORT_GPIO 0x00000000 /* Default general purpose IO usage */
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#define IOC_PORT_AON_CLK32K 0x00000007 /* AON External 32kHz clock */
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#define IOC_PORT_AUX_IO 0x00000008 /* AUX IO Pin */
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#define IOC_PORT_MCU_SSI0_RX 0x00000009 /* MCU SSI0 Receive Pin */
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#define IOC_PORT_MCU_SSI0_TX 0x0000000A /* MCU SSI0 Transmit Pin */
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#define IOC_PORT_MCU_SSI0_FSS 0x0000000B /* MCU SSI0 FSS Pin */
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#define IOC_PORT_MCU_SSI0_CLK 0x0000000C /* MCU SSI0 Clock Pin */
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#define IOC_PORT_MCU_I2C_MSSDA 0x0000000D /* MCU I2C Data Pin */
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#define IOC_PORT_MCU_I2C_MSSCL 0x0000000E /* MCU I2C Clock Pin */
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#define IOC_PORT_MCU_UART0_RX 0x0000000F /* MCU UART0 Receive Pin */
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#define IOC_PORT_MCU_UART0_TX 0x00000010 /* MCU UART0 Transmit Pin */
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#define IOC_PORT_MCU_UART0_CTS 0x00000011 /* MCU UART0 Clear To Send Pin */
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#define IOC_PORT_MCU_UART0_RTS 0x00000012 /* MCU UART0 Request To Send Pin */
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#define IOC_PORT_MCU_UART1_RX 0x00000013 /* MCU UART1 Receive Pin */
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#define IOC_PORT_MCU_UART1_TX 0x00000014 /* MCU UART1 Transmit Pin */
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#define IOC_PORT_MCU_UART1_CTS 0x00000015 /* MCU UART1 Clear To Send Pin */
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#define IOC_PORT_MCU_UART1_RTS 0x00000016 /* MCU UART1 Request To Send Pin */
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#define IOC_PORT_MCU_PORT_EVENT0 0x00000017 /* MCU PORT EVENT 0 */
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#define IOC_PORT_MCU_PORT_EVENT1 0x00000018 /* MCU PORT EVENT 1 */
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#define IOC_PORT_MCU_PORT_EVENT2 0x00000019 /* MCU PORT EVENT 2 */
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#define IOC_PORT_MCU_PORT_EVENT3 0x0000001A /* MCU PORT EVENT 3 */
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#define IOC_PORT_MCU_PORT_EVENT4 0x0000001B /* MCU PORT EVENT 4 */
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#define IOC_PORT_MCU_PORT_EVENT5 0x0000001C /* MCU PORT EVENT 5 */
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#define IOC_PORT_MCU_PORT_EVENT6 0x0000001D /* MCU PORT EVENT 6 */
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#define IOC_PORT_MCU_PORT_EVENT7 0x0000001E /* MCU PORT EVENT 7 */
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#define IOC_PORT_MCU_SWV 0x00000020 /* Serial Wire Viewer */
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#define IOC_PORT_MCU_SSI1_RX 0x00000021 /* MCU SSI1 Receive Pin */
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#define IOC_PORT_MCU_SSI1_TX 0x00000022 /* MCU SSI1 Transmit Pin */
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#define IOC_PORT_MCU_SSI1_FSS 0x00000023 /* MCU SSI1 FSS Pin */
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#define IOC_PORT_MCU_SSI1_CLK 0x00000024 /* MCU SSI1 Clock Pin */
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#define IOC_PORT_MCU_I2S_AD0 0x00000025 /* MCU I2S Data Pin 0 */
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#define IOC_PORT_MCU_I2S_AD1 0x00000026 /* MCU I2S Data Pin 1 */
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#define IOC_PORT_MCU_I2S_WCLK 0x00000027 /* MCU I2S Frame/Word Clock */
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#define IOC_PORT_MCU_I2S_BCLK 0x00000028 /* MCU I2S Bit Clock */
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#define IOC_PORT_MCU_I2S_MCLK 0x00000029 /* MCU I2S Master clock 2 */
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#define IOC_PORT_RFC_TRC 0x0000002E /* RF Core Tracer */
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#define IOC_PORT_RFC_GPO0 0x0000002F /* RC Core Data Out Pin 0 */
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#define IOC_PORT_RFC_GPO1 0x00000030 /* RC Core Data Out Pin 1 */
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#define IOC_PORT_RFC_GPO2 0x00000031 /* RC Core Data Out Pin 2 */
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#define IOC_PORT_RFC_GPO3 0x00000032 /* RC Core Data Out Pin 3 */
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#define IOC_PORT_RFC_GPI0 0x00000033 /* RC Core Data In Pin 0 */
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#define IOC_PORT_RFC_GPI1 0x00000034 /* RC Core Data In Pin 1 */
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#define IOC_PORT_RFC_SMI_DL_OUT 0x00000035 /* RF Core SMI Data Link Out */
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#define IOC_PORT_RFC_SMI_DL_IN 0x00000036 /* RF Core SMI Data Link in */
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#define IOC_PORT_RFC_SMI_CL_OUT 0x00000037 /* RF Core SMI Command Link Out */
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#define IOC_PORT_RFC_SMI_CL_IN 0x00000038 /* RF Core SMI Command Link In */
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#endif /* CC13XX_CC26XX_PINCTRL_COMMON_H_ */

‎soc/arm/ti_simplelink/cc13x2_cc26x2/pinctrl_soc.h‎

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/*
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* Copyright (c) 2022 Vaishnav Achath
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef TI_SIMPLELINK_CC13XX_CC26XX_SOC_PINCTRL_H_
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#define TI_SIMPLELINK_CC13XX_CC26XX_SOC_PINCTRL_H_
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#include <zephyr/types.h>
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/* Defines for enabling/disabling an IO */
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#define IOC_SLEW_ENABLE 0x00001000
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#define IOC_SLEW_DISABLE 0x00000000
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#define IOC_INPUT_ENABLE 0x20000000
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#define IOC_INPUT_DISABLE 0x00000000
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#define IOC_HYST_ENABLE 0x40000000
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#define IOC_HYST_DISABLE 0x00000000
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/* Defines that can be used to set the IO Mode of an IO */
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#define IOC_IOMODE_NORMAL 0x00000000
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#define IOC_IOMODE_INV 0x01000000
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#define IOC_IOMODE_OPEN_DRAIN_NORMAL 0x04000000
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#define IOC_IOMODE_OPEN_DRAIN_INV 0x05000000
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#define IOC_IOMODE_OPEN_SRC_NORMAL 0x06000000
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#define IOC_IOMODE_OPEN_SRC_INV 0x07000000
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/* Defines that can be used to set pull on an IO */
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#define IOC_NO_IOPULL 0x00006000
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#define IOC_IOPULL_UP 0x00004000
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#define IOC_IOPULL_DOWN 0x00002000
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typedef struct pinctrl_soc_pin_t {
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uint32_t pin;
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uint32_t iofunc;
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uint32_t iomode;
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} pinctrl_soc_pin_t;
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/* Convert DT flags to SoC flags */
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#define CC13XX_CC26XX_PIN_FLAGS(node_id) \
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(DT_PROP(node_id, bias_pull_up) * IOC_IOPULL_UP | \
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DT_PROP(node_id, bias_pull_down) * IOC_IOPULL_DOWN | \
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DT_PROP(node_id, bias_disable) * IOC_NO_IOPULL | \
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DT_PROP(node_id, drive_open_drain) * IOC_IOMODE_OPEN_DRAIN_NORMAL | \
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DT_PROP(node_id, drive_open_source) * IOC_IOMODE_OPEN_SRC_NORMAL | \
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DT_PROP(node_id, input_enable) * IOC_INPUT_ENABLE | \
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DT_PROP(node_id, input_schmitt_enable) * IOC_HYST_ENABLE)
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#define CC13XX_CC26XX_DT_PIN(node_id) \
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{ \
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.pin = DT_PROP_BY_IDX(node_id, pinmux, 0), \
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.iofunc = DT_PROP_BY_IDX(node_id, pinmux, 1), \
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.iomode = CC13XX_CC26XX_PIN_FLAGS(node_id) \
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},
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#define Z_PINCTRL_STATE_PIN_INIT(node_id, prop, idx) \
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CC13XX_CC26XX_DT_PIN(DT_PROP_BY_IDX(node_id, prop, idx))
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#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
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{ DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) }
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#endif /* TI_SIMPLELINK_CC13XX_CC26XX_SOC_PINCTRL_H_ */

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