@@ -35,25 +35,25 @@ LOG_MODULE_REGISTER(gpio_esp32, CONFIG_LOG_DEFAULT_LEVEL);
3535#define out_w1ts out_w1ts.val
3636#define out_w1tc out_w1tc.val
3737/* arch_curr_cpu() is not available for riscv based chips */
38- #define CPU_ID () 0
38+ #define ESP32_CPU_ID () 0
3939#elif CONFIG_SOC_SERIES_ESP32C3
4040/* gpio structs in esp32c3 series are different from xtensa ones */
4141#define out out.data
4242#define in in.data
4343#define out_w1ts out_w1ts.val
4444#define out_w1tc out_w1tc.val
4545/* arch_curr_cpu() is not available for riscv based chips */
46- #define CPU_ID () 0
46+ #define ESP32_CPU_ID () 0
4747#elif defined(CONFIG_SOC_SERIES_ESP32C6 )
4848/* gpio structs in esp32c6 are also different */
4949#define out out.out_data_orig
5050#define in in.in_data_next
5151#define out_w1ts out_w1ts.val
5252#define out_w1tc out_w1tc.val
5353/* arch_curr_cpu() is not available for riscv based chips */
54- #define CPU_ID () 0
54+ #define ESP32_CPU_ID () 0
5555#else
56- #define CPU_ID () arch_curr_cpu()->id
56+ #define ESP32_CPU_ID () arch_curr_cpu()->id
5757#endif
5858
5959#ifndef SOC_GPIO_SUPPORT_RTC_INDEPENDENT
@@ -413,7 +413,7 @@ static int gpio_esp32_pin_interrupt_configure(const struct device *port,
413413 }
414414
415415 gpio_ll_set_intr_type (cfg -> gpio_base , io_pin , intr_trig_mode );
416- gpio_ll_intr_enable_on_core (cfg -> gpio_base , CPU_ID (), io_pin );
416+ gpio_ll_intr_enable_on_core (cfg -> gpio_base , ESP32_CPU_ID (), io_pin );
417417 irq_unlock (key );
418418
419419 return 0 ;
@@ -432,7 +432,7 @@ static uint32_t gpio_esp32_get_pending_int(const struct device *dev)
432432{
433433 const struct gpio_esp32_config * const cfg = dev -> config ;
434434 uint32_t irq_status ;
435- uint32_t const core_id = CPU_ID ();
435+ uint32_t const core_id = ESP32_CPU_ID ();
436436
437437 if (cfg -> gpio_port == 0 ) {
438438 gpio_ll_get_intr_status (cfg -> gpio_base , core_id , & irq_status );
@@ -448,7 +448,7 @@ static void IRAM_ATTR gpio_esp32_fire_callbacks(const struct device *dev)
448448 const struct gpio_esp32_config * const cfg = dev -> config ;
449449 struct gpio_esp32_data * data = dev -> data ;
450450 uint32_t irq_status ;
451- uint32_t const core_id = CPU_ID ();
451+ uint32_t const core_id = ESP32_CPU_ID ();
452452
453453 if (cfg -> gpio_port == 0 ) {
454454 gpio_ll_get_intr_status (cfg -> gpio_base , core_id , & irq_status );
0 commit comments