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drivers: mdio: sy1xx add support for mdio
Add mdio support for the sensry soc sy1xx. Signed-off-by: Sven Ginka <[email protected]>
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‎drivers/mdio/CMakeLists.txt

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@@ -18,3 +18,4 @@ zephyr_library_sources_ifdef(CONFIG_MDIO_NXP_ENET_QOS mdio_nxp_enet_qos.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_DWCXGMAC mdio_dwcxgmac.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_RENESAS_RA mdio_renesas_ra.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_LAN865X mdio_lan865x.c)
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zephyr_library_sources_ifdef(CONFIG_MDIO_SENSRY_SY1XX mdio_sy1xx.c)

‎drivers/mdio/Kconfig

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@@ -39,6 +39,7 @@ source "drivers/mdio/Kconfig.nxp_enet_qos"
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source "drivers/mdio/Kconfig.dwcxgmac"
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source "drivers/mdio/Kconfig.renesas_ra"
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source "drivers/mdio/Kconfig.lan865x"
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source "drivers/mdio/Kconfig.sy1xx"
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config MDIO_INIT_PRIORITY
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int "Init priority"

‎drivers/mdio/Kconfig.sy1xx

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# Copyright (c) 2024 sensry.io
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# SPDX-License-Identifier: Apache-2.0
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config MDIO_SENSRY_SY1XX
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bool "Sensry SY1XX MDIO driver"
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select PINCTRL
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depends on DT_HAS_SENSRY_SY1XX_MDIO_ENABLED
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default y
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help
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Enable Sensry SY1xx SOC Family MDIO driver.

‎drivers/mdio/mdio_shell.c

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@@ -43,6 +43,8 @@ LOG_MODULE_REGISTER(mdio_shell, CONFIG_LOG_DEFAULT_LEVEL);
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#define DT_DRV_COMPAT st_stm32_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(snps_dwcxgmac_mdio)
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#define DT_DRV_COMPAT snps_dwcxgmac_mdio
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#elif DT_HAS_COMPAT_STATUS_OKAY(sensry_sy1xx_mdio)
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#define DT_DRV_COMPAT sensry_sy1xx_mdio
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#else
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#error "No known devicetree compatible match for MDIO shell"
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#endif

‎drivers/mdio/mdio_sy1xx.c

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/*
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* Copyright (c) 2024 sensry.io
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#define DT_DRV_COMPAT sensry_sy1xx_mdio
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#include <zephyr/logging/log.h>
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LOG_MODULE_REGISTER(sy1xx_mdio, CONFIG_MDIO_LOG_LEVEL);
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#include <zephyr/drivers/mdio.h>
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#include <zephyr/kernel.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <udma.h>
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struct sy1xx_mdio_dev_config {
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const struct pinctrl_dev_config *pcfg;
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uint32_t base_addr;
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uint32_t mdc_freq;
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};
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struct sy1xx_mdio_dev_data {
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struct k_sem sem;
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};
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/* mdio register offsets */
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#define SY1XX_MDIO_CFG_REG 0x0000
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#define SY1XX_MDIO_CTRL_REG 0x0004
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#define SY1XX_MDIO_READ_DATA_REG 0x0008
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#define SY1XX_MDIO_WRITE_DATA_REG 0x000c
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#define SY1XX_MDIO_IRQ_REG 0x0010
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/* mdio config register bit offsets */
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#define SY1XX_MDIO_CFG_DIV_OFFS (0)
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#define SY1XX_MDIO_CFG_EN_OFFS (8)
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/* mdio ctrl register bit offsets */
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#define SY1XX_MDIO_CTRL_READY_OFFS (0)
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#define SY1XX_MDIO_CTRL_INIT_OFFS (8)
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#define SY1XX_MDIO_CTRL_REG_ADDR_OFFS (16)
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#define SY1XX_MDIO_CTRL_PHY_ADDR_OFFS (24)
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#define SY1XX_MDIO_CTRL_OP_OFFS (30)
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/* mdio ctrl operations */
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#define SY1XX_MDIO_CTRL_OP_WRITE (0x1)
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#define SY1XX_MDIO_CTRL_OP_READ (0x2)
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#define SY1XX_MDIO_READ_WRITE_WAIT_TIME_US (15)
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#define SY1XX_MDIO_READ_WRITE_RETRY_COUNT (5)
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static int sy1xx_mdio_wait_for_ready(const struct device *dev);
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static int sy1xx_mdio_initialize(const struct device *dev)
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{
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struct sy1xx_mdio_dev_config *cfg = (struct sy1xx_mdio_dev_config *)dev->config;
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int ret;
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uint32_t divider;
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uint32_t reg;
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/* zero mdio controller regs */
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sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_CFG_REG);
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sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_CTRL_REG);
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sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_READ_DATA_REG);
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sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_WRITE_DATA_REG);
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sys_write32(0x0, cfg->base_addr + SY1XX_MDIO_IRQ_REG);
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/* prepare mdio clock and enable mdio controller */
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divider = (((sy1xx_soc_get_peripheral_clock() / cfg->mdc_freq) / 2) - 1) & 0xff;
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reg = (divider << SY1XX_MDIO_CFG_DIV_OFFS) | BIT(SY1XX_MDIO_CFG_EN_OFFS);
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LOG_DBG("config, div: %d, freq: %d", divider, cfg->mdc_freq);
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sys_write32(reg, cfg->base_addr + SY1XX_MDIO_CFG_REG);
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/* PAD config */
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ret = pinctrl_apply_state(cfg->pcfg, PINCTRL_STATE_DEFAULT);
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if (ret < 0) {
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LOG_ERR("failed to configure pins");
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return ret;
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}
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ret = sy1xx_mdio_wait_for_ready(dev);
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if (ret < 0) {
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LOG_ERR("not ready");
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return ret;
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}
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return 0;
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}
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static uint32_t sy1xx_mdio_is_ready(const struct device *dev)
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{
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struct sy1xx_mdio_dev_config *cfg = (struct sy1xx_mdio_dev_config *)dev->config;
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uint32_t status = sys_read32(cfg->base_addr + SY1XX_MDIO_CTRL_REG);
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return (status & BIT(SY1XX_MDIO_CTRL_READY_OFFS));
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}
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static int sy1xx_mdio_wait_for_ready(const struct device *dev)
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{
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uint32_t retries_left = SY1XX_MDIO_READ_WRITE_RETRY_COUNT;
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while (!sy1xx_mdio_is_ready(dev)) {
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k_sleep(K_USEC(SY1XX_MDIO_READ_WRITE_WAIT_TIME_US));
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retries_left--;
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if (!retries_left) {
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return -EINVAL;
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}
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}
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return 0;
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}
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static int sy1xx_mdio_read(const struct device *dev, uint8_t prtad, uint8_t regad, uint16_t *data)
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{
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struct sy1xx_mdio_dev_config *cfg = (struct sy1xx_mdio_dev_config *)dev->config;
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int ret;
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uint32_t v;
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prtad &= 0x1f;
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regad &= 0x1f;
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v = (SY1XX_MDIO_CTRL_OP_READ << SY1XX_MDIO_CTRL_OP_OFFS) |
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(prtad << SY1XX_MDIO_CTRL_PHY_ADDR_OFFS) | (regad << SY1XX_MDIO_CTRL_REG_ADDR_OFFS) |
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BIT(SY1XX_MDIO_CTRL_INIT_OFFS);
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/* start the reading procedure */
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sys_write32(v, cfg->base_addr + SY1XX_MDIO_CTRL_REG);
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/* wait for the reading operation to finish */
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ret = sy1xx_mdio_wait_for_ready(dev);
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if (ret < 0) {
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*data = sys_read32(cfg->base_addr + SY1XX_MDIO_READ_DATA_REG);
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LOG_WRN("timeout while reading from phy: %d, reg: %d, val: %d", prtad, regad,
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*data);
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return ret;
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}
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/* get the data from the read result register */
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*data = sys_read32(cfg->base_addr + SY1XX_MDIO_READ_DATA_REG);
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return 0;
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}
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static int sy1xx_mdio_write(const struct device *dev, uint8_t prtad, uint8_t regad, uint16_t data)
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{
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struct sy1xx_mdio_dev_config *cfg = (struct sy1xx_mdio_dev_config *)dev->config;
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int ret;
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uint32_t v;
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prtad &= 0x1f;
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regad &= 0x1f;
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/* put the data to the write register */
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sys_write32(data, cfg->base_addr + SY1XX_MDIO_WRITE_DATA_REG);
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v = (SY1XX_MDIO_CTRL_OP_WRITE << SY1XX_MDIO_CTRL_OP_OFFS) |
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(prtad << SY1XX_MDIO_CTRL_PHY_ADDR_OFFS) | (regad << SY1XX_MDIO_CTRL_REG_ADDR_OFFS) |
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BIT(SY1XX_MDIO_CTRL_INIT_OFFS);
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/* start the writing procedure */
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sys_write32(v, cfg->base_addr + SY1XX_MDIO_CTRL_REG);
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/* wait for the writing operation to finish */
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ret = sy1xx_mdio_wait_for_ready(dev);
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if (ret < 0) {
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LOG_WRN("timeout while writing to phy: %d, reg: %d, val: %d", prtad, regad, data);
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return ret;
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}
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return 0;
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}
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static DEVICE_API(mdio, sy1xx_mdio_driver_api) = {
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.read = sy1xx_mdio_read,
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.write = sy1xx_mdio_write,
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};
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#define SY1XX_MDIO_INIT(n) \
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\
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PINCTRL_DT_INST_DEFINE(n); \
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\
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static const struct sy1xx_mdio_dev_config sy1xx_mdio_dev_config_##n = { \
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.base_addr = DT_INST_REG_ADDR(n), \
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.pcfg = PINCTRL_DT_INST_DEV_CONFIG_GET(n), \
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.mdc_freq = DT_INST_PROP(n, clock_frequency), \
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}; \
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\
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static struct sy1xx_mdio_dev_data sy1xx_mdio_dev_data##n; \
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\
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DEVICE_DT_INST_DEFINE(n, &sy1xx_mdio_initialize, NULL, &sy1xx_mdio_dev_data##n, \
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&sy1xx_mdio_dev_config_##n, POST_KERNEL, CONFIG_MDIO_INIT_PRIORITY, \
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&sy1xx_mdio_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(SY1XX_MDIO_INIT)

‎dts/bindings/mdio/sensry,sy1xx-mdio.yaml

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# Copyright (c) 2024 sensry.io
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# SPDX-License-Identifier: Apache-2.0
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description: Sensry SY1XX MDIO Driver node
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compatible: "sensry,sy1xx-mdio"
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include: [base.yaml, mdio-controller.yaml, pinctrl-device.yaml]
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properties:
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reg:
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required: true
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pinctrl-0:
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required: true
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pinctrl-names:
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required: true

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