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soc: mcxw: Add Power Management support
Add PM support for MCXW SoC's Signed-off-by: Mahesh Mahadevan <[email protected]>
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‎soc/nxp/mcx/mcxw/Kconfig‎

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@@ -18,3 +18,4 @@ config SOC_FAMILY_MCXW
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select SOC_EARLY_INIT_HOOK
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select CLOCK_CONTROL
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select HAS_SEGGER_RTT if ZEPHYR_SEGGER_MODULE
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select HAS_PM

‎soc/nxp/mcx/mcxw/mcxw7xx/CMakeLists.txt‎

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@@ -10,6 +10,10 @@ zephyr_sources_ifdef(CONFIG_NXP_NBU
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../../../common/nxp_nbu.c
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)
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zephyr_sources_ifdef(CONFIG_PM
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power.c
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)
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zephyr_include_directories(./)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

‎soc/nxp/mcx/mcxw/mcxw7xx/Kconfig.defconfig‎

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@@ -8,8 +8,13 @@ config NUM_IRQS
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default 77 if SOC_MCXW727C
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default 75
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config MCUX_LPTMR_TIMER
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default y if PM
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DT_LPTMR_PATH := $(dt_nodelabel_path,lptmr0)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default 96000000 if CORTEX_M_SYSTICK
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default $(dt_node_int_prop_int,$(DT_LPTMR_PATH),clock-frequency) if MCUX_LPTMR_TIMER
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config MCUX_FLASH_K4_API
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default y

‎soc/nxp/mcx/mcxw/mcxw7xx/power.c‎

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@@ -0,0 +1,140 @@
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/*
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* Copyright 2025 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/kernel.h>
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#include <zephyr/pm/pm.h>
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#include "fsl_cmc.h"
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#include "fsl_spc.h"
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#include "fsl_vbat.h"
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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
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/*
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* 1. Set power mode protection
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* 2. Disable low power mode debug
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* 3. Enable Flash Doze mode.
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*/
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static void set_cmc_configuration(void)
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{
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CMC_SetPowerModeProtection(CMC0, kCMC_AllowAllLowPowerModes);
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CMC_LockPowerModeProtectionSetting(CMC0);
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#ifdef CONFIG_DEBUG
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CMC_EnableDebugOperation(CMC0, true);
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#else
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CMC_EnableDebugOperation(CMC0, false);
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#endif
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CMC_ConfigFlashMode(CMC0, false, false, false);
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}
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/*
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* Disable Backup SRAM regulator, FRO16K and Bandgap which
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* locates in VBAT power domain for most of power modes.
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*
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*/
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static void deinit_vbat(void)
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{
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VBAT_EnableBackupSRAMRegulator(VBAT0, false);
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VBAT_EnableFRO16k(VBAT0, false);
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while (VBAT_CheckFRO16kEnabled(VBAT0)) {
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};
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VBAT_EnableBandgap(VBAT0, false);
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while (VBAT_CheckBandgapEnabled(VBAT0)) {
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};
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}
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/* Invoke Low Power/System Off specific Tasks */
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__weak void pm_state_set(enum pm_state state, uint8_t substate_id)
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{
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/* Set PRIMASK */
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__disable_irq();
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/* Set BASEPRI to 0 */
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irq_unlock(0);
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if (state == PM_STATE_RUNTIME_IDLE) {
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k_cpu_idle();
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return;
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}
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set_cmc_configuration();
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deinit_vbat();
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switch (state) {
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case PM_STATE_SUSPEND_TO_IDLE:
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cmc_power_domain_config_t config;
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if (substate_id == 0) {
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/* Set NBU into Sleep Mode */
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RFMC->RF2P4GHZ_CTRL = (RFMC->RF2P4GHZ_CTRL &
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(~RFMC_RF2P4GHZ_CTRL_LP_MODE_MASK)) |
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RFMC_RF2P4GHZ_CTRL_LP_MODE(0x1);
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RFMC->RF2P4GHZ_CTRL |= RFMC_RF2P4GHZ_CTRL_LP_ENTER_MASK;
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/* Set MAIN_CORE and MAIN_WAKE power domain into sleep mode. */
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config.clock_mode = kCMC_GateAllSystemClocksEnterLowPowerMode;
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config.main_domain = kCMC_SleepMode;
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config.wake_domain = kCMC_SleepMode;
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CMC_EnterLowPowerMode(CMC0, &config);
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} else if (substate_id == 1) {
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} else {
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/* Nothing to do */
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}
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break;
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case PM_STATE_STANDBY:
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/* Enable CORE VDD Voltage scaling. */
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SPC_EnableLowPowerModeCoreVDDInternalVoltageScaling(SPC0, true);
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/* Set NBU into Deep Sleep Mode */
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RFMC->RF2P4GHZ_CTRL = (RFMC->RF2P4GHZ_CTRL & (~RFMC_RF2P4GHZ_CTRL_LP_MODE_MASK)) |
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RFMC_RF2P4GHZ_CTRL_LP_MODE(0x3);
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RFMC->RF2P4GHZ_CTRL |= RFMC_RF2P4GHZ_CTRL_LP_ENTER_MASK;
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/* Set MAIN_CORE and MAIN_WAKE power domain into Deep Sleep Mode. */
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config.clock_mode = kCMC_GateAllSystemClocksEnterLowPowerMode;
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config.main_domain = kCMC_DeepSleepMode;
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config.wake_domain = kCMC_DeepSleepMode;
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CMC_EnterLowPowerMode(CMC0, &config);
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break;
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default:
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LOG_DBG("Unsupported power state %u", state);
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break;
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}
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}
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/* Handle SOC specific activity after Low Power Mode Exit */
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__weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
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{
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ARG_UNUSED(state);
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ARG_UNUSED(substate_id);
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/* Clear PRIMASK */
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__enable_irq();
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if (state == PM_STATE_RUNTIME_IDLE) {
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return;
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}
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if (SPC_CheckPowerDomainLowPowerRequest(SPC0, kSPC_PowerDomain0)) {
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SPC_ClearPowerDomainLowPowerRequestFlag(SPC0, kSPC_PowerDomain0);
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}
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if (SPC_CheckPowerDomainLowPowerRequest(SPC0, kSPC_PowerDomain1)) {
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SPC_ClearPowerDomainLowPowerRequestFlag(SPC0, kSPC_PowerDomain1);
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}
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if (SPC_CheckPowerDomainLowPowerRequest(SPC0, kSPC_PowerDomain2)) {
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RFMC->RF2P4GHZ_CTRL = (RFMC->RF2P4GHZ_CTRL & (~RFMC_RF2P4GHZ_CTRL_LP_MODE_MASK));
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RFMC->RF2P4GHZ_CTRL &= ~RFMC_RF2P4GHZ_CTRL_LP_ENTER_MASK;
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SPC_ClearPowerDomainLowPowerRequestFlag(SPC0, kSPC_PowerDomain2);
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}
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SPC_ClearLowPowerRequest(SPC0);
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}
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void nxp_mcxw7x_power_init(void)
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{
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/* Enable LPTMR0 as wakeup source */
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NXP_ENABLE_WAKEUP_SIGNAL(0);
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}

‎soc/nxp/mcx/mcxw/mcxw7xx/soc.c‎

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@@ -15,6 +15,7 @@
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#include <fsl_ccm32k.h>
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#include <fsl_common.h>
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#include <fsl_clock.h>
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#include "fsl_spc.h"
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1920
extern uint32_t SystemCoreClock;
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extern void nxp_nbu_init(void);
@@ -221,6 +222,75 @@ static void vbat_init(void)
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base->STATUSA |= VBAT_STATUSA_POR_DET_MASK;
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};
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#if CONFIG_PM
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/*
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* In active mode, all HVDs/LVDs are disabled.
228+
* DCDC regulated to 1.8V, Core LDO regulated to 1.1V;
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* In low power modes, all HVDs/LVDs are disabled.
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* Bandgap is disabled, DCDC regulated to 1.25V, Core LDO regulated to 1.05V.
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*/
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__weak void set_spc_configuration(void)
234+
{
235+
/* Disable LVDs and HVDs in Active mode. */
236+
SPC_EnableActiveModeCoreHighVoltageDetect(SPC0, false);
237+
SPC_EnableActiveModeCoreLowVoltageDetect(SPC0, false);
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SPC_EnableActiveModeSystemHighVoltageDetect(SPC0, false);
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SPC_EnableActiveModeSystemLowVoltageDetect(SPC0, false);
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SPC_EnableActiveModeIOHighVoltageDetect(SPC0, false);
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SPC_EnableActiveModeIOLowVoltageDetect(SPC0, false);
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while (SPC_GetBusyStatusFlag(SPC0)) {
244+
}
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spc_active_mode_regulators_config_t active_mode_regulator;
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active_mode_regulator.bandgapMode = kSPC_BandgapEnabledBufferDisabled;
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active_mode_regulator.lpBuff = false;
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/* DCDC regulate to 1.8V. */
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active_mode_regulator.DCDCOption.DCDCVoltage = kSPC_DCDC_SafeModeVoltage;
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active_mode_regulator.DCDCOption.DCDCDriveStrength = kSPC_DCDC_NormalDriveStrength;
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active_mode_regulator.SysLDOOption.SysLDOVoltage = kSPC_SysLDO_NormalVoltage;
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active_mode_regulator.SysLDOOption.SysLDODriveStrength = kSPC_SysLDO_NormalDriveStrength;
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/* Core LDO regulate to 1.1V. */
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active_mode_regulator.CoreLDOOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
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#if defined(FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS) && FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS
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active_mode_regulator.CoreLDOOption.CoreLDODriveStrength = kSPC_CoreLDO_NormalDriveStrength;
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#endif /* FSL_FEATURE_SPC_HAS_CORELDO_VDD_DS */
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SPC_SetActiveModeDCDCRegulatorConfig(SPC0, &active_mode_regulator.DCDCOption);
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while (SPC_GetBusyStatusFlag(SPC0)) {
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}
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SPC_SetActiveModeSystemLDORegulatorConfig(SPC0, &active_mode_regulator.SysLDOOption);
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SPC_SetActiveModeBandgapModeConfig(SPC0, active_mode_regulator.bandgapMode);
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SPC_SetActiveModeCoreLDORegulatorConfig(SPC0, &active_mode_regulator.CoreLDOOption);
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SPC_EnableActiveModeCMPBandgapBuffer(SPC0, active_mode_regulator.lpBuff);
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spc_lowpower_mode_regulators_config_t low_power_regulator;
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low_power_regulator.lpIREF = false;
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low_power_regulator.bandgapMode = kSPC_BandgapDisabled;
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low_power_regulator.lpBuff = false;
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low_power_regulator.CoreIVS = false;
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low_power_regulator.DCDCOption.DCDCVoltage = kSPC_DCDC_LowUnderVoltage;
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low_power_regulator.DCDCOption.DCDCDriveStrength = kSPC_DCDC_LowDriveStrength;
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low_power_regulator.SysLDOOption.SysLDODriveStrength = kSPC_SysLDO_LowDriveStrength;
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low_power_regulator.CoreLDOOption.CoreLDOVoltage = kSPC_CoreLDO_MidDriveVoltage;
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low_power_regulator.CoreLDOOption.CoreLDODriveStrength = kSPC_CoreLDO_LowDriveStrength;
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SPC_SetLowPowerModeRegulatorsConfig(SPC0, &low_power_regulator);
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SPC_SetLowPowerWakeUpDelay(SPC0, 0xFFFFU);
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}
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#endif
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extern void nxp_mcxw7x_power_init(void);
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void soc_early_init_hook(void)
225295
{
226296
unsigned int oldLevel; /* old interrupt lock level */
@@ -234,6 +304,11 @@ void soc_early_init_hook(void)
234304
/* Smart power switch initialization */
235305
vbat_init();
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#if CONFIG_PM
308+
nxp_mcxw7x_power_init();
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set_spc_configuration();
310+
#endif
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/* restore interrupt state */
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irq_unlock(oldLevel);
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‎soc/nxp/mcx/mcxw/mcxw7xx/soc.h‎

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@@ -8,9 +8,14 @@
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#include <fsl_port.h>
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#include <soc_common.h>
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#include <fsl_wuu.h>
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1213
#define PORT_MUX_GPIO kPORT_MuxAsGpio
1314

1415
#define nbu_handler RF_IMU0_IRQHandler
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#undef NXP_ENABLE_WAKEUP_SIGNAL
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#define NXP_ENABLE_WAKEUP_SIGNAL(sig) WUU_SetInternalWakeUpModulesConfig(WUU0,\
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sig, kWUU_InternalModuleInterrupt);
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#endif /* _SOC__H_ */

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