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arch: arm: Separate common exc header file
This commit Separate exc.h into two header files, 'cortex_a_r/exc.h' and 'cortex_m/exc.h'. Still, keep 'exc.h' so that we don't need to change other files which include it. Signed-off-by: Huifeng Zhang <[email protected]>
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-144
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3 files changed

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‎include/zephyr/arch/arm/cortex_a_r/exc.h‎

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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM AArch32 Cortex-A and Cortex-R public exception handling
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_
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#ifdef _ASMLANGUAGE
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GTEXT(z_arm_exc_exit);
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#else
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
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#endif
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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/* Registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine calls.
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*
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* Registers s0-s15 (d0-d7, q0-q3) do not have to be preserved (and can be used
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* for passing arguments or returning results in standard procedure-call variants).
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*
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* Registers d16-d31 (q8-q15), do not have to be preserved.
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*/
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struct __fpu_sf {
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uint32_t s[16]; /* s0~s15 (d0-d7) */
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#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32
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uint64_t d[16]; /* d16~d31 */
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#endif
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uint32_t fpscr;
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uint32_t undefined;
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};
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#endif
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/* Additional register state that is not stacked by hardware on exception
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* entry.
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*
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* These fields are ONLY valid in the ESF copy passed into z_arm_fatal_error().
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* When information for a member is unavailable, the field is set to zero.
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*/
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
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struct __extra_esf_info {
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_callee_saved_t *callee;
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uint32_t msp;
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uint32_t exc_return;
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};
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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struct __esf {
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
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struct __extra_esf_info extra_info;
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#endif
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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struct __fpu_sf fpu;
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#endif
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struct __basic_sf {
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sys_define_gpr_with_alias(a1, r0);
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sys_define_gpr_with_alias(a2, r1);
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sys_define_gpr_with_alias(a3, r2);
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sys_define_gpr_with_alias(a4, r3);
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sys_define_gpr_with_alias(ip, r12);
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sys_define_gpr_with_alias(lr, r14);
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sys_define_gpr_with_alias(pc, r15);
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uint32_t xpsr;
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} basic;
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};
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extern uint32_t z_arm_coredump_fault_sp;
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typedef struct __esf z_arch_esf_t;
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extern void z_arm_exc_exit(bool fatal);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_A_R_EXC_H_ */

‎include/zephyr/arch/arm/cortex_m/exc.h‎

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/*
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* Copyright (c) 2013-2014 Wind River Systems, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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/**
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* @file
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* @brief ARM AArch32 Cortex-M public exception handling
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*/
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#ifndef ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_
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#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_
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#include <zephyr/devicetree.h>
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#include <zephyr/arch/arm/cortex_m/nvic.h>
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/* for assembler, only works with constants */
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#define Z_EXC_PRIO(pri) (((pri) << (8 - NUM_IRQ_PRIO_BITS)) & 0xff)
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/*
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* In architecture variants with non-programmable fault exceptions
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* (e.g. Cortex-M Baseline variants), hardware ensures processor faults
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* are given the highest interrupt priority level. SVCalls are assigned
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* the highest configurable priority level (level 0); note, however, that
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* this interrupt level may be shared with HW interrupts.
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*
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* In Cortex variants with programmable fault exception priorities we
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* assign the highest interrupt priority level (level 0) to processor faults
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* with configurable priority.
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* The highest priority level may be shared with either Zero-Latency IRQs (if
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* support for the feature is enabled) or with SVCall priority level.
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* Regular HW IRQs are always assigned priority levels lower than the priority
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* levels for SVCalls, Zero-Latency IRQs and processor faults.
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*
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* PendSV IRQ (which is used in Cortex-M variants to implement thread
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* context-switching) is assigned the lowest IRQ priority level.
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*/
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#if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS)
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#define _EXCEPTION_RESERVED_PRIO 1
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#else
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#define _EXCEPTION_RESERVED_PRIO 0
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#endif
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#define _EXC_FAULT_PRIO 0
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#define _EXC_ZERO_LATENCY_IRQS_PRIO 0
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#define _EXC_SVC_PRIO COND_CODE_1(CONFIG_ZERO_LATENCY_IRQS, \
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(CONFIG_ZERO_LATENCY_LEVELS), (0))
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#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + _EXC_SVC_PRIO)
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#define IRQ_PRIO_LOWEST (BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET) - 1)
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#define _EXC_IRQ_DEFAULT_PRIO Z_EXC_PRIO(_IRQ_PRIO_OFFSET)
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/* Use lowest possible priority level for PendSV */
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#define _EXC_PENDSV_PRIO 0xff
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#define _EXC_PENDSV_PRIO_MASK Z_EXC_PRIO(_EXC_PENDSV_PRIO)
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#ifdef _ASMLANGUAGE
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GTEXT(z_arm_exc_exit);
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#else
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#include <zephyr/types.h>
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#ifdef __cplusplus
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extern "C" {
66+
#endif
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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70+
/* Registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine calls.
71+
*
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* Registers s0-s15 (d0-d7, q0-q3) do not have to be preserved (and can be used
73+
* for passing arguments or returning results in standard procedure-call variants).
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*
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* Registers d16-d31 (q8-q15), do not have to be preserved.
76+
*/
77+
struct __fpu_sf {
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uint32_t s[16]; /* s0~s15 (d0-d7) */
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#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32
80+
uint64_t d[16]; /* d16~d31 */
81+
#endif
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uint32_t fpscr;
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uint32_t undefined;
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};
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#endif
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/* Additional register state that is not stacked by hardware on exception
88+
* entry.
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*
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* These fields are ONLY valid in the ESF copy passed into z_arm_fatal_error().
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* When information for a member is unavailable, the field is set to zero.
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*/
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
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struct __extra_esf_info {
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_callee_saved_t *callee;
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uint32_t msp;
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uint32_t exc_return;
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};
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#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
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struct __esf {
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struct __basic_sf {
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sys_define_gpr_with_alias(a1, r0);
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sys_define_gpr_with_alias(a2, r1);
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sys_define_gpr_with_alias(a3, r2);
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sys_define_gpr_with_alias(a4, r3);
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sys_define_gpr_with_alias(ip, r12);
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sys_define_gpr_with_alias(lr, r14);
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sys_define_gpr_with_alias(pc, r15);
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uint32_t xpsr;
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} basic;
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#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
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struct __fpu_sf fpu;
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#endif
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#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
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struct __extra_esf_info extra_info;
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#endif
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};
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extern uint32_t z_arm_coredump_fault_sp;
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typedef struct __esf z_arch_esf_t;
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extern void z_arm_exc_exit(void);
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#ifdef __cplusplus
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}
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#endif
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#endif /* _ASMLANGUAGE */
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#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_CORTEX_M_EXC_H_ */

‎include/zephyr/arch/arm/exc.h‎

Lines changed: 4 additions & 144 deletions
Original file line numberDiff line numberDiff line change
@@ -16,151 +16,11 @@
1616
#define ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_
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1818
#if defined(CONFIG_CPU_CORTEX_M)
19-
#include <zephyr/devicetree.h>
20-
21-
#include <zephyr/arch/arm/cortex_m/nvic.h>
22-
23-
/* for assembler, only works with constants */
24-
#define Z_EXC_PRIO(pri) (((pri) << (8 - NUM_IRQ_PRIO_BITS)) & 0xff)
25-
26-
/*
27-
* In architecture variants with non-programmable fault exceptions
28-
* (e.g. Cortex-M Baseline variants), hardware ensures processor faults
29-
* are given the highest interrupt priority level. SVCalls are assigned
30-
* the highest configurable priority level (level 0); note, however, that
31-
* this interrupt level may be shared with HW interrupts.
32-
*
33-
* In Cortex variants with programmable fault exception priorities we
34-
* assign the highest interrupt priority level (level 0) to processor faults
35-
* with configurable priority.
36-
* The highest priority level may be shared with either Zero-Latency IRQs (if
37-
* support for the feature is enabled) or with SVCall priority level.
38-
* Regular HW IRQs are always assigned priority levels lower than the priority
39-
* levels for SVCalls, Zero-Latency IRQs and processor faults.
40-
*
41-
* PendSV IRQ (which is used in Cortex-M variants to implement thread
42-
* context-switching) is assigned the lowest IRQ priority level.
43-
*/
44-
#if defined(CONFIG_CPU_CORTEX_M_HAS_PROGRAMMABLE_FAULT_PRIOS)
45-
#define _EXCEPTION_RESERVED_PRIO 1
19+
#include <zephyr/arch/arm/cortex_m/exc.h>
20+
#elif defined(CONFIG_CPU_AARCH32_CORTEX_A) || defined(CONFIG_CPU_AARCH32_CORTEX_R)
21+
#include <zephyr/arch/arm/cortex_a_r/exc.h>
4622
#else
47-
#define _EXCEPTION_RESERVED_PRIO 0
48-
#endif
49-
50-
#define _EXC_FAULT_PRIO 0
51-
#define _EXC_ZERO_LATENCY_IRQS_PRIO 0
52-
#define _EXC_SVC_PRIO COND_CODE_1(CONFIG_ZERO_LATENCY_IRQS, \
53-
(CONFIG_ZERO_LATENCY_LEVELS), (0))
54-
#define _IRQ_PRIO_OFFSET (_EXCEPTION_RESERVED_PRIO + _EXC_SVC_PRIO)
55-
#define IRQ_PRIO_LOWEST (BIT(NUM_IRQ_PRIO_BITS) - (_IRQ_PRIO_OFFSET) - 1)
56-
57-
#define _EXC_IRQ_DEFAULT_PRIO Z_EXC_PRIO(_IRQ_PRIO_OFFSET)
58-
59-
/* Use lowest possible priority level for PendSV */
60-
#define _EXC_PENDSV_PRIO 0xff
61-
#define _EXC_PENDSV_PRIO_MASK Z_EXC_PRIO(_EXC_PENDSV_PRIO)
23+
#error Unknown ARM architecture
6224
#endif /* CONFIG_CPU_CORTEX_M */
6325

64-
#ifdef _ASMLANGUAGE
65-
GTEXT(z_arm_exc_exit);
66-
#else
67-
#include <zephyr/types.h>
68-
69-
#ifdef __cplusplus
70-
extern "C" {
71-
#endif
72-
73-
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
74-
75-
/* Registers s16-s31 (d8-d15, q4-q7) must be preserved across subroutine calls.
76-
*
77-
* Registers s0-s15 (d0-d7, q0-q3) do not have to be preserved (and can be used
78-
* for passing arguments or returning results in standard procedure-call variants).
79-
*
80-
* Registers d16-d31 (q8-q15), do not have to be preserved.
81-
*/
82-
struct __fpu_sf {
83-
uint32_t s[16]; /* s0~s15 (d0-d7) */
84-
#ifdef CONFIG_VFP_FEATURE_REGS_S64_D32
85-
uint64_t d[16]; /* d16~d31 */
86-
#endif
87-
uint32_t fpscr;
88-
uint32_t undefined;
89-
};
90-
#endif
91-
92-
/* Additional register state that is not stacked by hardware on exception
93-
* entry.
94-
*
95-
* These fields are ONLY valid in the ESF copy passed into z_arm_fatal_error().
96-
* When information for a member is unavailable, the field is set to zero.
97-
*/
98-
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
99-
struct __extra_esf_info {
100-
_callee_saved_t *callee;
101-
uint32_t msp;
102-
uint32_t exc_return;
103-
};
104-
#endif /* CONFIG_EXTRA_EXCEPTION_INFO */
105-
106-
#if defined(CONFIG_CPU_CORTEX_M)
107-
108-
struct __esf {
109-
struct __basic_sf {
110-
sys_define_gpr_with_alias(a1, r0);
111-
sys_define_gpr_with_alias(a2, r1);
112-
sys_define_gpr_with_alias(a3, r2);
113-
sys_define_gpr_with_alias(a4, r3);
114-
sys_define_gpr_with_alias(ip, r12);
115-
sys_define_gpr_with_alias(lr, r14);
116-
sys_define_gpr_with_alias(pc, r15);
117-
uint32_t xpsr;
118-
} basic;
119-
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
120-
struct __fpu_sf fpu;
121-
#endif
122-
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
123-
struct __extra_esf_info extra_info;
124-
#endif
125-
};
126-
127-
#else
128-
129-
struct __esf {
130-
#if defined(CONFIG_EXTRA_EXCEPTION_INFO)
131-
struct __extra_esf_info extra_info;
132-
#endif
133-
#if defined(CONFIG_FPU) && defined(CONFIG_FPU_SHARING)
134-
struct __fpu_sf fpu;
135-
#endif
136-
struct __basic_sf {
137-
sys_define_gpr_with_alias(a1, r0);
138-
sys_define_gpr_with_alias(a2, r1);
139-
sys_define_gpr_with_alias(a3, r2);
140-
sys_define_gpr_with_alias(a4, r3);
141-
sys_define_gpr_with_alias(ip, r12);
142-
sys_define_gpr_with_alias(lr, r14);
143-
sys_define_gpr_with_alias(pc, r15);
144-
uint32_t xpsr;
145-
} basic;
146-
};
147-
148-
#endif
149-
150-
extern uint32_t z_arm_coredump_fault_sp;
151-
152-
typedef struct __esf z_arch_esf_t;
153-
154-
#ifdef CONFIG_CPU_CORTEX_M
155-
extern void z_arm_exc_exit(void);
156-
#else
157-
extern void z_arm_exc_exit(bool fatal);
158-
#endif
159-
160-
#ifdef __cplusplus
161-
}
162-
#endif
163-
164-
#endif /* _ASMLANGUAGE */
165-
16626
#endif /* ZEPHYR_INCLUDE_ARCH_ARM_AARCH32_EXC_H_ */

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