soc: x86: raptor_lake: Add GPIO support for rpl_crb

Enabled GPIO support for rpl_crb board by adding
platform GPIO specific definitions.

Signed-off-by: Anisetti Avinash Krishna <[email protected]>

Author: akanisetti

soc/x86/raptor_lake/soc.h

@@ -21,6 +21,10 @@
 #include <zephyr/random/rand32.h>
 #endif
 
+#ifdef CONFIG_GPIO_INTEL
+#include "soc_gpio.h"
+#endif
+
 #if DT_ON_BUS(DT_CHOSEN(zephyr_console), pcie)
 #include <zephyr/drivers/pcie/pcie.h>
 #define X86_SOC_EARLY_SERIAL_PCIDEV DT_REG_ADDR(DT_CHOSEN(zephyr_console))

soc/x86/raptor_lake/soc_gpio.h

@@ -0,0 +1,53 @@
+/*
+ * Copyright (c) 2023, Intel Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/**
+ * @file
+ * @brief GPIO macros for the Raptor Lake SoC
+ *
+ * This header file is used to specify the GPIO macros for
+ * the Raptor Lake SoC.
+ */
+
+#ifndef __SOC_GPIO_H_
+#define __SOC_GPIO_H_
+
+#define GPIO_INTEL_NR_SUBDEVS		13
+
+#define REG_PAD_OWNER_BASE		0x00A0
+#define REG_GPI_INT_STS_BASE		0x0200
+#define PAD_CFG0_PMODE_MASK		(0x07 << 10)
+
+#define REG_GPI_INT_EN_BASE		0x0220
+#define REG_PAD_HOST_SW_OWNER		0x150
+#define PAD_BASE_ADDR_MASK              0xfff
+
+#define GPIO_REG_BASE(reg_base) \
+	(reg_base & ~PAD_BASE_ADDR_MASK)
+
+#define GPIO_PAD_BASE(reg_base) \
+	(reg_base & PAD_BASE_ADDR_MASK)
+
+#define GPIO_PAD_OWNERSHIP(raw_pin, pin_offset)					\
+	(pin_offset % 8) ?							\
+		REG_PAD_OWNER_BASE +						\
+			 ((((pin_offset / 8) + 1) + (raw_pin / 8)) * 0x4) :	\
+		REG_PAD_OWNER_BASE +						\
+			 (((pin_offset / 8) + (raw_pin / 8)) * 0x4);		\
+
+#define GPIO_OWNERSHIP_BIT(raw_pin) ((raw_pin % 8) * 4)
+
+#define GPIO_RAW_PIN(pin, pin_offset) pin
+
+#define GPIO_INTERRUPT_BASE(cfg) \
+	(cfg->group_index * 0x4)
+
+#define GPIO_BASE(cfg) \
+	(cfg->group_index * 0x4)
+
+#define PIN_OFFSET 0x10
+
+#endif /* __SOC_GPIO_H_ */