boards: renesas: Add SPI support for Renesas RZ/V2L, A3UL

Add SPI support for board Renesas RZ/V2L-SMARC, RZ/A3UL-SMARC

Signed-off-by: Hieu Nguyen <[email protected]>
Signed-off-by: Nhut Nguyen <[email protected]>

Author: Hieu Nguyen

boards/renesas/rza3ul_smarc/rza3ul_smarc-pinctrl.dtsi

@@ -34,4 +34,13 @@
 			input-enable;
 		};
 	};
+
+	/omit-if-no-ref/ spi0_pins: spi0 {
+		spi0-pinmux {
+			pinmux = <RZA_PINMUX(PORT_01, 0, 2)>, /* CK */
+				 <RZA_PINMUX(PORT_02, 2, 6)>, /* MOSI */
+				 <RZA_PINMUX(PORT_02, 3, 6)>, /* MISO */
+				 <RZA_PINMUX(PORT_01, 3, 2)>; /* SSL */
+		};
+	};
 };

boards/renesas/rza3ul_smarc/rza3ul_smarc.dts

@@ -81,6 +81,12 @@
 	status = "okay";
 };
 
+&spi0 {
+	pinctrl-0 = <&spi0_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};
+
 &wdt0 {
 	status = "okay";
 };

boards/renesas/rza3ul_smarc/rza3ul_smarc.yaml

@@ -11,6 +11,7 @@ supported:
   - pwm
   - adc
   - i2c
+  - spi
   - counter
   - watchdog
 testing:

boards/renesas/rzv2l_smarc/rzv2l_smarc-pinctrl.dtsi

@@ -32,4 +32,13 @@
 				 <RZV_PINMUX(PORT_18, 1, 3)>; /* SCL */
 		};
 	};
+
+	/omit-if-no-ref/ spi1_pins: spi1 {
+		spi1-pinmux {
+			pinmux = <RZV_PINMUX(PORT_44, 0, 1)>, /* CK */
+				 <RZV_PINMUX(PORT_44, 1, 1)>, /* MOSI */
+				 <RZV_PINMUX(PORT_44, 2, 1)>, /* MISO */
+				 <RZV_PINMUX(PORT_44, 3, 1)>; /* SSL */
+		};
+	};
 };

boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.dts

@@ -43,3 +43,9 @@
 	pinctrl-names = "default";
 	status = "okay";
 };
+
+&spi1 {
+	pinctrl-0 = <&spi1_pins>;
+	pinctrl-names = "default";
+	status = "okay";
+};

boards/renesas/rzv2l_smarc/rzv2l_smarc_r9a07g054l23gbg_cm33.yaml

@@ -11,6 +11,7 @@ supported:
   - pwm
   - adc
   - i2c
+  - spi
   - counter
   - mbox
 vendor: renesas