soc: st: stm32n6: Provide static mpu regions for !XIP

In !XIP case, provide RAM_RO and RAM_RW regions with their
respective MPU configurations.

Signed-off-by: Erwan Gouriou <[email protected]>
Co-authored-by: Sudan Landge <[email protected]>

Author: 2 people

soc/st/stm32/stm32n6x/CMakeLists.txt

@@ -11,6 +11,11 @@ zephyr_sources_ifdef(CONFIG_STM32N6_NPU
 
 zephyr_include_directories(.)
 
+if(CONFIG_CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS)
+  zephyr_linker_sources(SECTIONS mpu_regions.ld)
+  zephyr_sources(mpu_regions.c)
+endif()
+
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")
 
 zephyr_linker_sources_ifdef(CONFIG_BOOTLOADER_MCUBOOT SECTIONS ram_check.ld)

soc/st/stm32/stm32n6x/Kconfig

@@ -22,6 +22,7 @@ config SOC_SERIES_STM32N6X
 	select BUILD_OUTPUT_BIN
 	# MPU_GAP_FILLING is default when !USERSPACE, select it in the other case as well.
 	select MPU_GAP_FILLING if USERSPACE
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS if USERSPACE && !XIP
 
 config STM32N6_BOOT_SERIAL
 	bool "Serial boot target (USB)"

soc/st/stm32/stm32n6x/mpu_regions.c

@@ -0,0 +1,40 @@
+/*
+ * Copyright The Zephyr Project Contributors
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/linker/linker-defs.h>
+#include <zephyr/arch/arm/mpu/arm_mpu.h>
+
+extern const uint32_t __rom_region_limit[];
+extern const uint32_t __image_ram_limit[];
+
+static const struct arm_mpu_region mpu_regions[] = {
+	{
+		.base = (uint32_t)__rom_region_start,
+		.name = "SRAM_RO",
+		.attr = {
+			.rbar = RO_Msk | NON_SHAREABLE_Msk,
+			.mair_idx = MPU_MAIR_INDEX_FLASH,
+			.pxn = !PRIV_EXEC_NEVER,
+			.r_limit = (uint32_t)__rom_region_limit,
+		},
+	},
+	{
+		.base = (uint32_t)_image_ram_start,
+		.name = "SRAM_RW",
+		.attr = {
+			.rbar = NOT_EXEC | P_RW_U_NA_Msk | NON_SHAREABLE_Msk,
+			.mair_idx = MPU_MAIR_INDEX_SRAM,
+			.pxn = !PRIV_EXEC_NEVER,
+			.r_limit = (uint32_t)__image_ram_limit,
+		},
+	}
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};

soc/st/stm32/stm32n6x/mpu_regions.ld

@@ -0,0 +1,19 @@
+/*
+ * Copyright The Zephyr Project Contributors
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/** \brief MPU Region Base Address Register Definitions */
+#define MPU_RBAR_BASE_Pos		5					/*!< MPU RBAR: BASE Position */
+#define MPU_RBAR_BASE_Msk		(0x7FFFFFF << MPU_RBAR_BASE_Pos)	/*!< MPU RBAR: BASE Mask */
+
+/** \brief MPU Region Limit Address Register Definitions */
+#define MPU_RLAR_LIMIT_Pos		5					/*!< MPU RLAR: LIMIT Position */
+#define MPU_RLAR_LIMIT_Msk		(0x7FFFFFF << MPU_RLAR_LIMIT_Pos)	/*!< MPU RLAR: LIMIT Mask */
+
+#define REGION_LIMIT_ADDR(base, size) (((base & MPU_RBAR_BASE_Msk) + size - 1) & MPU_RLAR_LIMIT_Msk)
+
+PROVIDE(__rom_region_limit = REGION_LIMIT_ADDR(__rom_region_start, __rom_region_size));
+PROVIDE(__image_ram_limit = REGION_LIMIT_ADDR(_image_ram_start, (CONFIG_SRAM_SIZE * 1024)));