soc: st: stm32: stm32c0x: Add stop mode support

Enables low power stop mode for C0.

Code is taken from F4 family, tested on nucleo-c71rb with
samples/basic/blinky.

Power consumption in run mode 3.7 mA, in stop mode ~87 uA.

Signed-off-by: Tomáš Juřena <[email protected]>

Author: jurenat

soc/st/stm32/stm32c0x/CMakeLists.txt

@@ -6,6 +6,7 @@ zephyr_sources(
   )
 
 zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c)
+zephyr_sources_ifdef(CONFIG_PM power.c)
 
 zephyr_include_directories(.)
 

soc/st/stm32/stm32c0x/Kconfig

@@ -10,5 +10,6 @@ config SOC_SERIES_STM32C0X
 	select CPU_HAS_ARM_MPU
 	select HAS_STM32CUBE
 	select CPU_CORTEX_M_HAS_SYSTICK
+	select HAS_PM
 	select HAS_POWEROFF
 	select SOC_EARLY_INIT_HOOK

soc/st/stm32/stm32c0x/Kconfig.defconfig

@@ -7,4 +7,14 @@ if SOC_SERIES_STM32C0X
 
 rsource "Kconfig.defconfig.stm32c0*"
 
+if PM
+
+config COUNTER
+	default y
+
+config COUNTER_RTC_STM32_SUBSECONDS
+	default y if DT_HAS_ST_STM32_RTC_ENABLED
+
+endif # PM
+
 endif # SOC_SERIES_STM32C0X

soc/st/stm32/stm32c0x/power.c

@@ -0,0 +1,66 @@
+/*
+ * Copyright (c) 2023 Google LLC
+ * Copyright (c) 2025 Tomas Jurena
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <clock_control/clock_stm32_ll_common.h>
+#include <soc.h>
+
+#include <stm32c0xx_ll_cortex.h>
+#include <stm32c0xx_ll_pwr.h>
+#include <stm32c0xx.h>
+
+#include <zephyr/kernel.h>
+#include <zephyr/logging/log.h>
+
+LOG_MODULE_DECLARE(soc, CONFIG_SOC_LOG_LEVEL);
+
+BUILD_ASSERT(DT_SAME_NODE(DT_CHOSEN(zephyr_cortex_m_idle_timer), DT_NODELABEL(rtc)),
+		"STM32C0x series needs RTC as an additional IDLE timer for power management");
+
+void pm_state_set(enum pm_state state, uint8_t substate_id)
+{
+	ARG_UNUSED(substate_id);
+
+	switch (state) {
+	case PM_STATE_SUSPEND_TO_IDLE:
+		LL_LPM_DisableEventOnPend();
+		LL_PWR_ClearFlag_WU();
+
+		LL_PWR_SetPowerMode(LL_PWR_MODE_STOP0);
+		LL_LPM_EnableDeepSleep();
+
+		k_cpu_idle();
+
+		break;
+	default:
+		LOG_WRN("Unsupported power state %u", state);
+		break;
+	}
+}
+
+void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
+{
+	ARG_UNUSED(substate_id);
+
+	switch (state) {
+	case PM_STATE_SUSPEND_TO_IDLE:
+		LL_LPM_DisableSleepOnExit();
+		LL_LPM_EnableSleep();
+
+		/* Restore the clock setup. */
+		stm32_clock_control_init(NULL);
+		break;
+	default:
+		LOG_WRN("Unsupported power substate-id %u", state);
+		break;
+	}
+
+	/*
+	 * System is now in active mode. Reenable interrupts which were
+	 * disabled when OS started idling code.
+	 */
+	irq_unlock(0);
+}

soc/st/stm32/stm32c0x/soc.c

@@ -14,6 +14,7 @@
 #include <zephyr/linker/linker-defs.h>
 #include <string.h>
 
+#include <stm32_ll_bus.h>
 #include <stm32_ll_system.h>
 
 #include <cmsis_core.h>
@@ -32,4 +33,7 @@ void soc_early_init_hook(void)
 	/* Update CMSIS SystemCoreClock variable (HCLK) */
 	/* At reset, system core clock is set to 48 MHz from HSI */
 	SystemCoreClock = 48000000;
+
+	/* Enable PWR clock */
+	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }