adsp: boot: power: Separate watchdog state from core power

The watchdog is controlled by ll-scheduler and should not be resumed when
a core is bringing up. Watchdog pause control code was removed.

Signed-off-by: Adrian Warecki <[email protected]>

Author: softwarecki

soc/xtensa/intel_adsp/ace/include/intel_ace15_mtpm/adsp_boot.h

@@ -57,9 +57,6 @@ struct dspcs {
 #define DSPBR_BATTR_LPSCTL_L1_MIN_WAY			BIT(15)
 #define DSPBR_BATTR_LPSCTL_BATTR_SLAVE_CORE		BIT(16)
 
-#define DSPBR_WDT_RESUME				BIT(8)
-#define DSPBR_WDT_RESTART_COMMAND			0x76
-
 #define DSPCS (*(volatile struct dspcs *)DSPCS_REG)
 
 #endif /* ZEPHYR_SOC_INTEL_ADSP_BOOT_H_ */

soc/xtensa/intel_adsp/ace/multiprocessing.c

@@ -129,11 +129,6 @@ void soc_mp_startup(uint32_t cpu)
 	/* Prevent idle from powering us off */
 	DSPCS.bootctl[cpu].bctl |=
 		DSPBR_BCTL_WAITIPCG | DSPBR_BCTL_WAITIPPG;
-	/* checking if WDT was stopped during D3 transition */
-	if (DSPCS.bootctl[cpu].wdtcs & DSPBR_WDT_RESUME) {
-		DSPCS.bootctl[cpu].wdtcs = DSPBR_WDT_RESUME;
-		/* TODO: delete this IF when FW starts using imr restore vector */
-	}
 }
 
 void arch_sched_ipi(void)

soc/xtensa/intel_adsp/ace/power.c

@@ -221,7 +221,6 @@ __weak void pm_state_set(enum pm_state state, uint8_t substate_id)
 		core_desc[cpu].intenable = XTENSA_RSR("INTENABLE");
 		z_xt_ints_off(0xffffffff);
 		core_desc[cpu].bctl = DSPCS.bootctl[cpu].bctl;
-		DSPCS.bootctl[cpu].wdtcs = DSPBR_WDT_RESTART_COMMAND;
 		DSPCS.bootctl[cpu].bctl &= ~DSPBR_BCTL_WAITIPCG;
 		soc_cpus_active[cpu] = false;
 		z_xtensa_cache_flush_inv_all();
@@ -309,7 +308,6 @@ __weak void pm_state_exit_post_ops(enum pm_state state, uint8_t substate_id)
 	uint32_t cpu = arch_proc_id();
 
 	if (state == PM_STATE_SOFT_OFF) {
-		DSPCS.bootctl[cpu].wdtcs = DSPBR_WDT_RESUME;
 		/* restore clock gating state */
 		DSPCS.bootctl[cpu].bctl |=
 			(core_desc[0].bctl & DSPBR_BCTL_WAITIPCG);