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dts: infineon: pse84 device tree changes to support AutAnalog ADC
*Separates AutAnalog and AutAnalog ADC in device tree. *Makes AutAnalog SAR ADC a child of the AutAnalog system to reflect hardware architecture. *Adds binding file for AutAnalog SAR ADC driver. Signed-off-by: John Batch <[email protected]>
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-9
lines changed

4 files changed

+96
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lines changed

dts/arm/infineon/edge/pse84/pse84.cm55.dtsi

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interrupts = <19 4>;
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};
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&adc0 {
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&autanalog {
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interrupts = <36 4>;
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};
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dts/arm/infineon/edge/pse84/pse84.dtsi

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#gpio-cells = <2>;
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};
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adc0: adc@42e80000 {
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compatible = "infineon,autanalog-sar-adc";
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reg = <0x42e80000 0xf20>;
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autanalog: analog@42e00000 {
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reg = <0x42e00000 0x100000>;
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interrupts = <57 4>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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#io-channel-cells = <1>;
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ranges;
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adc0: adc0@80000 {
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compatible = "infineon,autanalog-sar-adc";
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/* Offset within AutAnalog subsystem */
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reg = <0x80000 0xf20>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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};
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ipc0: ipc@422a0000 {

dts/arm/infineon/edge/pse84/pse84_s.dtsi

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#gpio-cells = <2>;
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};
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adc0: adc@52e80000 {
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compatible = "infineon,autanalog-sar-adc";
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reg = <0x52e80000 0xf20>;
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autanalog: analog@52e00000 {
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reg = <0x52e00000 0x100000>;
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interrupts = <57 4>;
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status = "disabled";
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#address-cells = <1>;
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#size-cells = <1>;
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#io-channel-cells = <1>;
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ranges;
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adc0: adc0@80000 {
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compatible = "infineon,autanalog-sar-adc";
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/* Offset within AutAnalog subsystem */
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reg = <0x80000 0xf20>;
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status = "disabled";
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#io-channel-cells = <1>;
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};
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};
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ipc0: ipc@522a0000 {
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# Copyright (c) 2025 Infineon Technologies AG,
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# or an affiliate of Infineon Technologies AG.
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#
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# SPDX-License-Identifier: Apache-2.0
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title: PSOC Edge AutAnalog SAR ADC
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description: |
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Infineon PSOC Edge 84 AutAnalog SAR ADC
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The AutAnalog (Autonomous Analog) SAR ADC provides high resolution 12-bit analog-to-digital
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conversion capabilities for the PSOC Edge family of microcontrollers.
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The ADC provides 12-bit resolution with a sampling rate of up to 5Msps when configured in
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high performance mode. The inputs can be configured to sample directly from analog inputs or
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through an internal mux to select from signals from other AutAnalog peripherals.
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The AutAnalog SAR ADC is part of the AutAnalog subsystem, which must be set up before initializing
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the ADC. Additionally, the AutAnalog subsystem uses a shared interrupt which handles events from
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all AutAnalog peripherals.
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compatible: "infineon,autanalog-sar-adc"
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include: adc-controller.yaml
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properties:
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reg:
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required: true
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description: Base address of the AutAnalog SAR ADC Registers
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"#io-channel-cells":
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const: 1
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description: Number of cells in an io-channel specifier
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vref-mv:
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type: int
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default: 1800
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description: |
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Internal reference voltage in millivolts.
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offset-cal:
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type: boolean
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description: |
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Enables Self-Calibration for offset correction within the ADC. If left disabled,
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the factory calibration for offset correction will be used.
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linear-cal:
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type: boolean
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description: |
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Enables Self-Calibration for linearity correction within the ADC. If left disabled,
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the factory calibration for linearity will be used.
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vref-source:
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type: string
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default: "vdda"
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enum:
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- "vdda"
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- "external"
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- "vbgr"
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- "vdda_by_2"
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- "prb_out1"
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- "prb_out2"
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description: |
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Selects which voltage reference to use for the ADC.
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The default value of vdda matches the hardware default value and provides ADC
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functionality without requiring additional hardware.
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io-channel-cells:
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- input

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