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Tavish Naruka
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drivers: serial: add tms570 uart driver
Adds SCI peripheral UART driver for TMS570. Signed-off-by: Tavish Naruka <[email protected]>
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‎drivers/serial/CMakeLists.txt‎

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@@ -92,6 +92,7 @@ zephyr_library_sources_ifdef(CONFIG_UART_STELLARIS uart_stellaris.c)
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zephyr_library_sources_ifdef(CONFIG_UART_STM32 uart_stm32.c)
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zephyr_library_sources_ifdef(CONFIG_UART_SY1XX uart_sy1xx.c)
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zephyr_library_sources_ifdef(CONFIG_UART_TELINK_B91 uart_b91.c)
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zephyr_library_sources_ifdef(CONFIG_UART_TMS570 uart_tms570.c)
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zephyr_library_sources_ifdef(CONFIG_UART_WCH_USART uart_wch_usart.c)
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zephyr_library_sources_ifdef(CONFIG_UART_XEC uart_mchp_xec.c)
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zephyr_library_sources_ifdef(CONFIG_UART_XEN_HVC uart_hvc_xen.c)

‎drivers/serial/Kconfig‎

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@@ -232,6 +232,7 @@ rsource "Kconfig.stellaris"
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rsource "Kconfig.stm32"
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rsource "Kconfig.sy1xx"
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rsource "Kconfig.test"
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rsource "Kconfig.tms570"
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rsource "Kconfig.uart_sam"
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rsource "Kconfig.usart_sam"
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rsource "Kconfig.wch_usart"

‎drivers/serial/Kconfig.tms570‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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config UART_TMS570
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bool "TI TMS570 series SCI USART driver"
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default y
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depends on DT_HAS_TI_TMS570_UART_ENABLED
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select SERIAL_HAS_DRIVER
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select PINCTRL
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help
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This option enables the TMS570 UART driver.

‎drivers/serial/uart_tms570.c‎

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/*
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* Copyright (c) 2025 ispace, inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/device.h>
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#include <zephyr/devicetree.h>
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#include <zephyr/drivers/uart.h>
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#include <zephyr/drivers/pinctrl.h>
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#include <zephyr/arch/arm/cortex_a_r/sys_io.h>
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#define DT_DRV_COMPAT ti_tms570_uart
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#define VCLK_FREQUENCY DT_PROP(DT_NODELABEL(clk_vclk), clock_frequency)
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#define TMS570_GCR0 (0x00)
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#define TMS570_GCR1 (0x04)
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#define TMS570_GCR2 (0x08)
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#define TMS570_SETINT (0x0c)
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#define TMS570_CLEARINT (0x10)
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#define TMS570_SETINTLVL (0x14)
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#define TMS570_CLEARINTLVL (0x18)
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#define TMS570_FLR (0x1c)
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#define TMS570_INTVECT0 (0x20)
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#define TMS570_INTVECT1 (0x24)
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#define TMS570_FORMAT (0x28)
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#define TMS570_BRS (0x2c)
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#define TMS570_ED (0x30)
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#define TMS570_RD (0x34)
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#define TMS570_TD (0x38)
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#define TMS570_PIO0 (0x3c)
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#define TMS570_PIO1 (0x40)
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#define TMS570_PIO2 (0x44)
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#define TMS570_PIO3 (0x48)
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#define TMS570_PIO4 (0x4c)
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#define TMS570_PIO5 (0x50)
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#define TMS570_PIO6 (0x54)
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#define TMS570_PIO7 (0x58)
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#define TMS570_PIO8 (0x5c)
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#define TMS570_IODFTCTRL (0x90)
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#define TMS570_SCI_REG_GCR0 (dev_cfg->base_addr + TMS570_GCR0)
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#define TMS570_SCI_REG_GCR1 (dev_cfg->base_addr + TMS570_GCR1)
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#define TMS570_SCI_REG_CLEARINT (dev_cfg->base_addr + TMS570_CLEARINT)
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#define TMS570_SCI_REG_CLEARINTLVL (dev_cfg->base_addr + TMS570_CLEARINTLVL)
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#define TMS570_SCI_REG_FORMAT (dev_cfg->base_addr + TMS570_FORMAT)
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#define TMS570_SCI_REG_BRS (dev_cfg->base_addr + TMS570_BRS)
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#define TMS570_SCI_REG_FUNC (dev_cfg->base_addr + TMS570_PIO0)
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#define TMS570_SCI_REG_PIO8 (dev_cfg->base_addr + TMS570_PIO8)
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#define TMS570_SCI_REG_RD (dev_cfg->base_addr + TMS570_RD)
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#define TMS570_SCI_REG_TD (dev_cfg->base_addr + TMS570_TD)
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#define TMS570_SCI_REG_FLR (dev_cfg->base_addr + TMS570_FLR)
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#define GCR1_TXENA (1 << 25)
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#define GCR1_RXENA (1 << 24)
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#define GCR1_CONT (1 << 17)
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#define GCR1_LOOPBACK (1 << 16)
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#define GCR1_STOP_EXT_FRAME (1 << 13)
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#define GCR1_HGEN_CTRL (1 << 12)
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#define GCR1_CTYPE (1 << 11)
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#define GCR1_MBUF_MODE (1 << 10)
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#define GCR1_ADAPT (1 << 9)
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#define GCR1_SLEEP (1 << 8)
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#define GCR1_SWnRST (1 << 7)
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#define GCR1_LIN_MODE (1 << 6)
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#define GCR1_CLOCK (1 << 5)
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#define GCR1_STOP_BIT_1 (0 << 4)
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#define GCR1_STOP_BIT_2 (1 << 4)
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#define GCR1_PARITY_ENA (1 << 2)
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#define GCR1_PARITY_ODD ((0 << 3) | GCR1_PARITY_ENA)
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#define GCR1_PARITY_EVEN ((1 << 3) | GCR1_PARITY_ENA)
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#define GCR1_PARITY_NONE (0)
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#define GCR1_TIMING_MODE_SYNC (0 << 1)
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#define GCR1_TIMING_MODE_ASYNC (1 << 1)
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#define GCR1_COMM_MODE (1 << 0)
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#define FLR_RX_RDY (1 << 9)
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#define FLR_TX_RDY (1 << 8)
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#define FORMAT_CHARS_IN_FRAME(x) (((x - 1) & 0x7) << 16)
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#define FORMAT_BITS_PER_CHAR(x) (((x - 1) & 0x7))
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#define FORMAT_8_BIT_1_CHAR (FORMAT_CHARS_IN_FRAME(1) | FORMAT_BITS_PER_CHAR(8))
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#define PIO_TX_EN (1 << 2)
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#define PIO_RX_EN (1 << 1)
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/* Device data structure */
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struct uart_tms570_dev_cfg_t {
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const uint32_t base_addr; /* Register base address */
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const uint32_t baud_rate; /* Baud rate */
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const struct pinctrl_dev_config *pincfg;
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};
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static void uart_tms570_poll_out(const struct device *dev, uint8_t c)
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{
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const struct uart_tms570_dev_cfg_t *dev_cfg =
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(const struct uart_tms570_dev_cfg_t *) dev->config;
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while ((sys_read32(TMS570_SCI_REG_FLR) & 0x00000100U) == 0U) {
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/* wait */
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}
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sys_write32(c, TMS570_SCI_REG_TD);
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}
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static int uart_tms570_poll_in(const struct device *dev, uint8_t *c)
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{
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const struct uart_tms570_dev_cfg_t *dev_cfg =
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(const struct uart_tms570_dev_cfg_t *) dev->config;
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uint32_t flags;
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flags = sys_read32(TMS570_SCI_REG_FLR);
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if ((flags & FLR_RX_RDY) != 0) {
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*c = (uint8_t)sys_read32(TMS570_SCI_REG_RD);
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return 0;
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} else {
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return -1;
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}
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}
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static int uart_tms570_init(const struct device *dev)
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{
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const struct uart_tms570_dev_cfg_t *dev_cfg =
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(const struct uart_tms570_dev_cfg_t *) dev->config;
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/* reset SCI */
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sys_write32(0, TMS570_SCI_REG_GCR0);
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sys_write32(1, TMS570_SCI_REG_GCR0);
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/* enable and set up uart */
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sys_write32(GCR1_TXENA | GCR1_RXENA | /* enable both tx and rx */
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GCR1_CLOCK | /* internal clock (device has no clock pin) */
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GCR1_STOP_BIT_1 |
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GCR1_PARITY_NONE |
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GCR1_TIMING_MODE_ASYNC,
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TMS570_SCI_REG_GCR1);
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/* make pins SCI mode */
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sys_write32(PIO_TX_EN | PIO_RX_EN, TMS570_SCI_REG_FUNC);
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pinctrl_apply_state(dev_cfg->pincfg, PINCTRL_STATE_DEFAULT);
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/* baudrate */
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sys_write32(VCLK_FREQUENCY / ((dev_cfg->baud_rate - 1) * 16), TMS570_SCI_REG_BRS);
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/* we want 8 bit per char and 1 char per frame */
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sys_write32(FORMAT_8_BIT_1_CHAR, TMS570_SCI_REG_FORMAT);
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/* start */
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sys_write32(sys_read32(TMS570_SCI_REG_GCR1) | GCR1_SWnRST, TMS570_SCI_REG_GCR1);
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return 0;
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}
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static const struct uart_driver_api uart_tms570_driver_api = {
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.poll_in = uart_tms570_poll_in,
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.poll_out = uart_tms570_poll_out,
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.err_check = NULL,
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};
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#define TMS570_UART_INIT(idx) \
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PINCTRL_DT_INST_DEFINE(idx); \
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static struct uart_tms570_dev_cfg_t tms570__uart##idx##_cfg = { \
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.base_addr = DT_INST_REG_ADDR(idx), \
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.baud_rate = DT_INST_PROP(idx, current_speed), \
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.pincfg = PINCTRL_DT_INST_DEV_CONFIG_GET(idx), \
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}; \
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DEVICE_DT_INST_DEFINE(idx, &uart_tms570_init, NULL, NULL, \
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&tms570__uart##idx##_cfg, PRE_KERNEL_1, \
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CONFIG_SERIAL_INIT_PRIORITY, \
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&uart_tms570_driver_api);
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DT_INST_FOREACH_STATUS_OKAY(TMS570_UART_INIT)

‎dts/arm/ti/tms570.dtsi‎

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reg = <0xffff1c00 0x400>;
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status = "okay";
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};
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sci1: uart@fff7e400 {
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compatible = "ti,tms570-uart";
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reg = <0xfff7e400 256>;
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status = "disabled";
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};
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sci3: uart@fff7e500 {
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compatible = "ti,tms570-uart";
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reg = <0xfff7e500 256>;
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status = "disabled";
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};
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};
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};

‎dts/bindings/serial/ti,tms570-uart.yaml‎

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# Copyright (c) 2025, ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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description: TI TMS570 UART
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compatible: "ti,tms570-uart"
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include: [uart-controller.yaml, pinctrl-device.yaml, base.yaml]
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properties:
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reg:
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required: true

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