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Enjia Mainashif
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tests: interrupt: refine the interrupt testcases
This PR include 2 changes to refine the testcases: 1. Now we using IPI to trigger interrupt in testing instead of INT instruction, this means we don't need to hardcode the vector number. That can avoid some problem. Fixes: #40374 2. Refined the test cases. Tigger interrupt by INT instruction and IPI cannot be masked by irq_disabled(). Unless it's a external interrupt, such as a timer. Now remove those incorrect part of these testcases. Signed-off-by: Enjia Mai <[email protected]>
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+54
-119
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4 files changed

+54
-119
lines changed

tests/kernel/interrupt/src/direct_isr.c

Lines changed: 26 additions & 36 deletions
Original file line numberDiff line numberDiff line change
@@ -20,25 +20,13 @@
2020
#define TEST_DIRECT_IRQ_LINE_1 3
2121
#define TEST_DIRECT_IRQ_LINE_2 4
2222

23-
/* the vector got would be different when enable code coverage */
24-
#if defined(CONFIG_COVERAGE)
25-
#define TRIGGER_DIRECT_IRQ_LINE_1 34
26-
#define TRIGGER_DIRECT_IRQ_LINE_2 35
27-
#else
28-
#define TRIGGER_DIRECT_IRQ_LINE_1 35
29-
#define TRIGGER_DIRECT_IRQ_LINE_2 34
30-
#endif
31-
3223
#define TEST_DIRECT_IRQ_PRIO 0
3324

3425
#elif defined(CONFIG_ARCH_POSIX)
3526
#define TEST_DIRECT_IRQ_LINE_1 5
3627
#define TEST_DIRECT_IRQ_LINE_2 6
3728

38-
#define TRIGGER_DIRECT_IRQ_LINE_1 TEST_DIRECT_IRQ_LINE_1
39-
#define TRIGGER_DIRECT_IRQ_LINE_2 TEST_DIRECT_IRQ_LINE_2
40-
41-
#define TEST_DIRECT_IRQ_PRIO 1
29+
#define TEST_DIRECT_IRQ_PRIO 5
4230

4331
#endif
4432

@@ -81,55 +69,57 @@ void test_direct_interrupt(void)
8169
trig_vec1 = Z_IRQ_TO_INTERRUPT_VECTOR(TEST_DIRECT_IRQ_LINE_1);
8270
trig_vec2 = Z_IRQ_TO_INTERRUPT_VECTOR(TEST_DIRECT_IRQ_LINE_2);
8371
#elif defined(CONFIG_ARCH_POSIX)
84-
trig_vec1 = TRIGGER_DIRECT_IRQ_LINE_1;
85-
trig_vec2 = TRIGGER_DIRECT_IRQ_LINE_2;
72+
trig_vec1 = TEST_DIRECT_IRQ_LINE_1;
73+
trig_vec2 = TEST_DIRECT_IRQ_LINE_2;
8674
#endif
8775
TC_PRINT("irq(%d)=vector(%d)\n", TEST_DIRECT_IRQ_LINE_1, trig_vec1);
8876
TC_PRINT("irq(%d)=vector(%d)\n", TEST_DIRECT_IRQ_LINE_2, trig_vec2);
8977

90-
/* verify the target triggering vector is correct */
91-
zassert_equal(trig_vec1, TRIGGER_DIRECT_IRQ_LINE_1,
92-
"vector %d mismatch we specified to trigger %d",
93-
trig_vec1, TRIGGER_DIRECT_IRQ_LINE_1);
94-
95-
zassert_equal(trig_vec2, TRIGGER_DIRECT_IRQ_LINE_2,
96-
"vector %d mismatch we specified to trigger %d",
97-
trig_vec2, TRIGGER_DIRECT_IRQ_LINE_2);
98-
9978
irq_enable(TEST_DIRECT_IRQ_LINE_1);
10079
irq_enable(TEST_DIRECT_IRQ_LINE_2);
10180

10281
zassert_true(direct_int_executed[0] == 0 &&
10382
direct_int_executed[1] == 0,
10483
"Both ISR should not execute");
10584

106-
trigger_irq(TRIGGER_DIRECT_IRQ_LINE_1);
85+
trigger_irq(trig_vec1);
10786

10887
zassert_true(direct_int_executed[0] == 1 &&
10988
direct_int_executed[1] == 0,
11089
"ISR1 should execute");
11190

112-
trigger_irq(TRIGGER_DIRECT_IRQ_LINE_2);
91+
trigger_irq(trig_vec2);
11392

11493
zassert_true(direct_int_executed[0] == 1 &&
11594
direct_int_executed[1] == 1,
11695
"Both ISR should execute");
11796

118-
irq_disable(TEST_DIRECT_IRQ_LINE_1);
119-
irq_disable(TEST_DIRECT_IRQ_LINE_2);
97+
unsigned int key = irq_lock();
12098

121-
trigger_irq(TRIGGER_DIRECT_IRQ_LINE_1);
122-
trigger_irq(TRIGGER_DIRECT_IRQ_LINE_2);
99+
/* trigger under irq locked */
100+
trigger_irq(trig_vec1);
101+
trigger_irq(trig_vec2);
123102

124-
/*
125-
* irq_enable()/irq_disable() does not work here,
126-
* see #33901.
127-
*/
128-
#if !defined(CONFIG_X86)
129103
zassert_true(direct_int_executed[0] == 1 &&
130104
direct_int_executed[1] == 1,
131105
"Both ISR should not execute again");
132-
#endif
106+
107+
irq_unlock(key);
108+
109+
/* interrupt serve after irq unlocked */
110+
zassert_true(direct_int_executed[0] == 2 &&
111+
direct_int_executed[1] == 2,
112+
"Both ISR should execute again(%d)(%d)",
113+
direct_int_executed[0], direct_int_executed[1]);
114+
115+
/* trigger after irq unlocked */
116+
trigger_irq(trig_vec1);
117+
trigger_irq(trig_vec2);
118+
119+
zassert_true(direct_int_executed[0] == 3 &&
120+
direct_int_executed[1] == 3,
121+
"Both ISR should execute again(%d)(%d)",
122+
direct_int_executed[0], direct_int_executed[1]);
133123
}
134124
#else
135125
void test_direct_interrupt(void)

tests/kernel/interrupt/src/dynamic_isr.c

Lines changed: 9 additions & 34 deletions
Original file line numberDiff line numberDiff line change
@@ -18,7 +18,7 @@ static void dyn_isr(const void *arg)
1818
{
1919
ARG_UNUSED(arg);
2020
handler_test_result = (uintptr_t)arg;
21-
handler_has_run = 1;
21+
handler_has_run++;
2222
}
2323

2424
#if defined(CONFIG_GEN_SW_ISR_TABLE)
@@ -70,19 +70,10 @@ void test_isr_dynamic(void)
7070
*/
7171
#if defined(CONFIG_X86)
7272
#define IV_IRQS 32 /* start of vectors available for x86 IRQs */
73-
74-
/* Using APIC TSC deadline timer will conflict with our testcase */
75-
#if defined(CONFIG_APIC_TSC_DEADLINE_TIMER)
76-
#define TEST_IRQ_DYN_LINE 17
77-
#else
7873
#define TEST_IRQ_DYN_LINE 16
79-
#endif
80-
81-
#define TRIGGER_IRQ_DYN_LINE (TEST_IRQ_DYN_LINE + IV_IRQS)
8274

8375
#elif defined(CONFIG_ARCH_POSIX)
8476
#define TEST_IRQ_DYN_LINE 5
85-
#define TRIGGER_IRQ_DYN_LINE 5
8677
#endif
8778

8879
void test_isr_dynamic(void)
@@ -98,38 +89,21 @@ void test_isr_dynamic(void)
9889
extern void (*x86_irq_funcs[])(const void *);
9990
extern const void *x86_irq_args[];
10091

101-
zassert_true(x86_irq_funcs[TEST_IRQ_DYN_LINE] == dyn_isr &&
102-
x86_irq_args[TEST_IRQ_DYN_LINE] == (void *)ISR_DYN_ARG,
92+
zassert_true(x86_irq_funcs[vector_num - IV_IRQS] == dyn_isr &&
93+
x86_irq_args[vector_num - IV_IRQS] == (void *)ISR_DYN_ARG,
10394
"dynamic isr did not install successfully");
10495
#endif
10596

10697
TC_PRINT("vector(%d)\n", vector_num);
10798
zassert_true(vector_num > 0,
10899
"irq connect dynamic failed");
109100

110-
/*
111-
* The reason we need to hard code the trigger vector here
112-
* is that the x86 only support immediate number for INT
113-
* instruction. So trigger an interrupt of x86 under gcov code
114-
* coverage report enabled, which means GCC optimization will
115-
* be -O0. In this case, an build error happens and shows:
116-
* "error: 'asm' operand 0 probably does not match constraints"
117-
* and "error: impossible constraint in 'asm'"
118-
*
119-
* Although we hard code the trigger vecotr it here, we still
120-
* do a check if the vector match getting from
121-
* arch_irq_connect_dynamic().
122-
*/
123-
zassert_equal(vector_num, TRIGGER_IRQ_DYN_LINE,
124-
"vector %d mismatch we specified to trigger %d",
125-
vector_num, TRIGGER_IRQ_DYN_LINE);
126-
127101
zassert_equal(handler_has_run, 0,
128102
"handler has run before interrupt trigger");
129103

130104
irq_enable(TEST_IRQ_DYN_LINE);
131105

132-
trigger_irq(TRIGGER_IRQ_DYN_LINE);
106+
trigger_irq(vector_num);
133107

134108
zassert_equal(handler_has_run, 1,
135109
"interrupt triggered but handler has not run(%d)",
@@ -140,12 +114,13 @@ extern const void *x86_irq_args[];
140114
"parameter(0x%lx) in handler is not correct",
141115
handler_test_result);
142116

143-
irq_disable(TRIGGER_IRQ_DYN_LINE);
117+
trigger_irq(vector_num);
144118

145-
/**TESTPOINT: interrupt cannot be triggered when disable it */
146-
zassert_equal(handler_has_run, 1,
147-
"interrupt handler should not be triggered again(%d)",
119+
/**TESTPOINT: interrupt triggered again */
120+
zassert_equal(handler_has_run, 2,
121+
"interrupt triggered but handler has not run(%d)",
148122
handler_has_run);
123+
149124
}
150125
#endif /* CONFIG_GEN_SW_ISR_TABLE */
151126

tests/kernel/interrupt/src/interrupt_offload.c

Lines changed: 2 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -86,17 +86,13 @@ void isr_handler(const void *param)
8686
* Other arch will be add later.
8787
*/
8888
#if defined(CONFIG_X86)
89-
#define IV_IRQS 32
9089
#define TEST_IRQ_DYN_LINE 17
91-
#define TRIGGER_IRQ_DYN_LINE (TEST_IRQ_DYN_LINE + IV_IRQS)
9290

9391
#elif defined(CONFIG_ARCH_POSIX)
9492
#define TEST_IRQ_DYN_LINE 5
95-
#define TRIGGER_IRQ_DYN_LINE 5
9693

9794
#else
9895
#define TEST_IRQ_DYN_LINE 0
99-
#define TRIGGER_IRQ_DYN_LINE 0
10096
#endif
10197

10298
#endif
@@ -114,7 +110,7 @@ static void init_dyn_interrupt(void)
114110
isr_handler, (void *)&irq_param, 0);
115111
}
116112

117-
TC_PRINT("irq(%d)\n", vector_num);
113+
TC_PRINT("vector(%d)\n", vector_num);
118114
zassert_true(vector_num > 0, "no vector can be used");
119115
irq_enable(TEST_IRQ_DYN_LINE);
120116
}
@@ -124,7 +120,7 @@ static void trigger_offload_interrupt(const bool real_irq, void *work)
124120
irq_param.work = work;
125121

126122
if (real_irq) {
127-
trigger_irq(TRIGGER_IRQ_DYN_LINE);
123+
trigger_irq(vector_num);
128124
} else {
129125
irq_offload((irq_offload_routine_t)&isr_handler, &irq_param);
130126
}

tests/kernel/interrupt/src/regular_isr.c

Lines changed: 17 additions & 43 deletions
Original file line numberDiff line numberDiff line change
@@ -16,9 +16,6 @@
1616
#define TEST_IRQ_LINE_1 27
1717
#define TEST_IRQ_LINE_2 28
1818

19-
#define TRIGGER_IRQ_LINE_1 64
20-
#define TRIGGER_IRQ_LINE_2 65
21-
2219
#define TEST_IRQ_PRIO 2
2320

2421

@@ -61,58 +58,32 @@ void test_isr_regular(void)
6158
IRQ_CONNECT(TEST_IRQ_LINE_1, TEST_IRQ_PRIO, isr_comm, (void *)TEST_IRQ_LINE_1, 0);
6259
IRQ_CONNECT(TEST_IRQ_LINE_2, TEST_IRQ_PRIO, isr_comm, (void *)TEST_IRQ_LINE_2, 0);
6360

64-
#if defined(CONFIG_X86)
6561
trig_vec1 = Z_IRQ_TO_INTERRUPT_VECTOR(TEST_IRQ_LINE_1);
6662
trig_vec2 = Z_IRQ_TO_INTERRUPT_VECTOR(TEST_IRQ_LINE_2);
67-
#elif defined(CONFIG_ARCH_POSIX)
68-
trig_vec1 = TRIGGER_IRQ_LINE_1;
69-
trig_vec2 = TRIGGER_IRQ_LINE_2;
70-
#endif
71-
72-
/* verify the target triggering vector is correct */
73-
zassert_equal(trig_vec1, TRIGGER_IRQ_LINE_1,
74-
"vector %d mismatch we specified to trigger %d",
75-
trig_vec1, TRIGGER_IRQ_LINE_1);
76-
77-
zassert_equal(trig_vec2, TRIGGER_IRQ_LINE_2,
78-
"vector %d mismatch we specified to trigger %d",
79-
trig_vec2, TRIGGER_IRQ_LINE_2);
8063

8164
TC_PRINT("irq(%d)=vector(%d)\n", TEST_IRQ_LINE_1, trig_vec1);
8265
TC_PRINT("irq(%d)=vector(%d)\n", TEST_IRQ_LINE_2, trig_vec2);
8366

67+
irq_enable(TEST_IRQ_LINE_1);
68+
irq_enable(TEST_IRQ_LINE_2);
8469

85-
trigger_irq(TRIGGER_IRQ_LINE_1);
70+
trigger_irq(trig_vec1);
8671

8772
zassert_true(reg_int_executed[0] == 1 &&
8873
reg_int_executed[1] == 0,
8974
"ISR1 should execute");
9075

91-
trigger_irq(TRIGGER_IRQ_LINE_2);
76+
trigger_irq(trig_vec2);
9277

9378
zassert_true(reg_int_executed[0] == 1 &&
9479
reg_int_executed[1] == 1,
9580
"Both ISR should execute");
9681

97-
/* Skip checking here, see #33901 */
98-
#if !defined(CONFIG_X86)
99-
100-
irq_disable(TEST_IRQ_LINE_1);
101-
irq_disable(TEST_IRQ_LINE_2);
102-
103-
/* trigger under irq disabled */
104-
trigger_irq(TRIGGER_IRQ_LINE_1);
105-
trigger_irq(TRIGGER_IRQ_LINE_2);
106-
107-
zassert_true(reg_int_executed[0] == 1 &&
108-
reg_int_executed[1] == 1,
109-
"Both ISR should not execute again");
110-
111-
int key = irq_lock();
82+
unsigned int key = irq_lock();
11283

11384
/* trigger under irq locked */
114-
trigger_irq(TRIGGER_IRQ_LINE_1);
115-
trigger_irq(TRIGGER_IRQ_LINE_2);
85+
trigger_irq(trig_vec1);
86+
trigger_irq(trig_vec2);
11687

11788
zassert_true(reg_int_executed[0] == 1 &&
11889
reg_int_executed[1] == 1,
@@ -121,17 +92,20 @@ void test_isr_regular(void)
12192

12293
irq_unlock(key);
12394

124-
/* trigger under irq unlocked */
125-
trigger_irq(TRIGGER_IRQ_LINE_1);
126-
trigger_irq(TRIGGER_IRQ_LINE_2);
127-
95+
/* interrupt serve after irq unlocked */
12896
zassert_true(reg_int_executed[0] == 2 &&
12997
reg_int_executed[1] == 2,
13098
"Both ISR should execute again(%d)(%d)",
13199
reg_int_executed[0], reg_int_executed[1]);
132-
#else
133-
TC_PRINT("not testing irq enable/disable\n");
134-
#endif
100+
101+
/* trigger after irq unlocked */
102+
trigger_irq(trig_vec1);
103+
trigger_irq(trig_vec2);
104+
105+
zassert_true(reg_int_executed[0] == 3 &&
106+
reg_int_executed[1] == 3,
107+
"Both ISR should execute again(%d)(%d)",
108+
reg_int_executed[0], reg_int_executed[1]);
135109
}
136110
#else
137111
void test_isr_regular(void)

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