drivers: interrupt_controller: add stm32mp2 exti

Add the mp2 exti2 dts to the dtsi file.
Add mp2 exti hal and ll function calls with EXTI2 instance. We use the
EXTI2 instance because it contains the GPIO interrupts in the non-secure
context. (We are trying to build the blinky sample as a first milestone)

Signed-off-by: Youssef Zini <[email protected]>

Author: youssefz24

drivers/interrupt_controller/intc_exti_stm32.c

@@ -2,6 +2,7 @@
  * Copyright (c) 2016 Open-RnD Sp. z o.o.
  * Copyright (c) 2017 RnDity Sp. z o.o.
  * Copyright (c) 2019-23 Linaro Limited
+ * Copyright (C) 2025 Savoir-faire Linux, Inc.
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -60,7 +61,8 @@ static inline uint32_t stm32_exti_linenum_to_src_cfg_line(gpio_pin_t linenum)
 #if defined(CONFIG_SOC_SERIES_STM32L0X) || \
 	defined(CONFIG_SOC_SERIES_STM32F0X)
 	return ((linenum % 4 * 4) << 16) | (linenum / 4);
-#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti)
+#elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32g0_exti) || \
+	defined(CONFIG_SOC_SERIES_STM32MP2X)
 	return ((linenum & 0x3) << (16 + 3)) | (linenum >> 2);
 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
 	/* Gives the LL_SBS_EXTI_LINEn corresponding to the line number */
@@ -82,6 +84,9 @@ static inline int stm32_exti_is_pending(stm32_gpio_irq_line_t line)
 		LL_EXTI_IsActiveFallingFlag_0_31(line));
 #elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
 	return LL_C2_EXTI_IsActiveFlag_0_31(line);
+#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
+	return LL_EXTI_IsActiveRisingFlag_0_31(EXTI2, line) ||
+		LL_EXTI_IsActiveFallingFlag_0_31(EXTI2, line);
 #else
 	return LL_EXTI_IsActiveFlag_0_31(line);
 #endif
@@ -99,6 +104,9 @@ static inline void stm32_exti_clear_pending(stm32_gpio_irq_line_t line)
 	LL_EXTI_ClearFallingFlag_0_31(line);
 #elif defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
 	LL_C2_EXTI_ClearFlag_0_31(line);
+#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
+	LL_EXTI_ClearRisingFlag_0_31(EXTI2, line);
+	LL_EXTI_ClearFallingFlag_0_31(EXTI2, line);
 #else
 	LL_EXTI_ClearFlag_0_31(line);
 #endif
@@ -269,6 +277,8 @@ void stm32_gpio_intc_enable_line(stm32_gpio_irq_line_t line)
 	/* Enable requested line interrupt */
 #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
 	LL_C2_EXTI_EnableIT_0_31(line);
+#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
+	LL_C2_EXTI_EnableIT_0_31(EXTI2, line);
 #else
 	LL_EXTI_EnableIT_0_31(line);
 #endif
@@ -281,6 +291,8 @@ void stm32_gpio_intc_disable_line(stm32_gpio_irq_line_t line)
 {
 #if defined(CONFIG_SOC_SERIES_STM32H7X) && defined(CONFIG_CPU_CORTEX_M4)
 	LL_C2_EXTI_DisableIT_0_31(line);
+#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
+	LL_C2_EXTI_DisableIT_0_31(EXTI2, line);
 #else
 	LL_EXTI_DisableIT_0_31(line);
 #endif
@@ -291,6 +303,24 @@ void stm32_gpio_intc_select_line_trigger(stm32_gpio_irq_line_t line, uint32_t tr
 	z_stm32_hsem_lock(CFG_HW_EXTI_SEMID, HSEM_LOCK_DEFAULT_RETRY);
 
 	switch (trg) {
+#if defined(CONFIG_SOC_SERIES_STM32MP2X)
+	case STM32_GPIO_IRQ_TRIG_NONE:
+		LL_EXTI_DisableRisingTrig_0_31(EXTI2, line);
+		LL_EXTI_DisableFallingTrig_0_31(EXTI2, line);
+		break;
+	case STM32_GPIO_IRQ_TRIG_RISING:
+		LL_EXTI_EnableRisingTrig_0_31(EXTI2, line);
+		LL_EXTI_DisableFallingTrig_0_31(EXTI2, line);
+		break;
+	case STM32_GPIO_IRQ_TRIG_FALLING:
+		LL_EXTI_EnableFallingTrig_0_31(EXTI2, line);
+		LL_EXTI_DisableRisingTrig_0_31(EXTI2, line);
+		break;
+	case STM32_GPIO_IRQ_TRIG_BOTH:
+		LL_EXTI_EnableRisingTrig_0_31(EXTI2, line);
+		LL_EXTI_EnableFallingTrig_0_31(EXTI2, line);
+		break;
+#else /* CONFIG_SOC_SERIES_STM32MP2X */
 	case STM32_GPIO_IRQ_TRIG_NONE:
 		LL_EXTI_DisableRisingTrig_0_31(line);
 		LL_EXTI_DisableFallingTrig_0_31(line);
@@ -307,6 +337,7 @@ void stm32_gpio_intc_select_line_trigger(stm32_gpio_irq_line_t line, uint32_t tr
 		LL_EXTI_EnableRisingTrig_0_31(line);
 		LL_EXTI_EnableFallingTrig_0_31(line);
 		break;
+#endif /* CONFIG_SOC_SERIES_STM32MP2X */
 	default:
 		__ASSERT_NO_MSG(0);
 		break;
@@ -369,6 +400,8 @@ void stm32_exti_set_line_src_port(gpio_pin_t line, uint32_t port)
 	LL_EXTI_SetEXTISource(port, ll_line);
 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
 	LL_SBS_SetEXTISource(port, ll_line);
+#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
+	LL_EXTI_SetEXTISource(EXTI2, port, ll_line);
 #else
 	LL_SYSCFG_SetEXTISource(port, ll_line);
 #endif
@@ -386,6 +419,8 @@ uint32_t stm32_exti_get_line_src_port(gpio_pin_t line)
 	port = LL_EXTI_GetEXTISource(ll_line);
 #elif DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7rs_exti)
 	port = LL_SBS_GetEXTISource(ll_line);
+#elif defined(CONFIG_SOC_SERIES_STM32MP2X)
+	port = LL_EXTI_GetEXTISource(EXTI2, ll_line);
 #else
 	port = LL_SYSCFG_GetEXTISource(ll_line);
 #endif

dts/arm/st/mp2/stm32mp2_m33.dtsi

@@ -35,6 +35,27 @@
 			#clock-cells = <2>;
 			reg = <0x44200000 DT_SIZE_K(64)>;
 		};
+
+		exti2: interrupt-controller@46230000 {
+			compatible = "st,stm32-exti";
+			interrupt-controller;
+			#interrupt-cells = <1>;
+			#address-cells = <1>;
+			reg = <0x46230000 DT_SIZE_K(1)>;
+			num-lines = <16>;
+			interrupts = <17 0>, <18 0>, <19 0>, <20 0>,
+					 <21 0>, <22 0>, <23 0>, <24 0>,
+					 <25 0>, <26 0>, <27 0>, <28 0>,
+					 <29 0>, <30 0>, <31 0>, <32 0>;
+			interrupt-names = "line0", "line1", "line2", "line3",
+					  "line4", "line5", "line6", "line7",
+					  "line8", "line9", "line10", "line11",
+					  "line12", "line13", "line14", "line15";
+			line-ranges = <0 1>, <1 1>, <2 1>, <3 1>,
+				      <4 1>, <5 1>, <6 1>, <7 1>,
+				      <8 1>, <9 1>, <10 1>, <11 1>,
+				      <12 1>, <13 1>, <14 1>, <15 1>;
+		};
 	};
 };