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facchinmkartben
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boards: add support for Arduino Portenta C33
Tested: * GPIO * UART * USB (using USB_DEVICE_NEXT) * BLE Signed-off-by: Martino Facchin <[email protected]> Signed-off-by: Luca Burelli <[email protected]>
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# Copyright 2025 Arduino SA
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# SPDX-License-Identifier: Apache-2.0
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zephyr_sources_ifdef(CONFIG_NETWORKING eth_clock.c)
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# Copyright (c) 2025 Arduino SA
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# SPDX-License-Identifier: Apache-2.0
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config BOARD_ARDUINO_PORTENTA_C33
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select SOC_R7FA6M5BH3CFC
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# Copyright 2025 Arduino SA
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# SPDX-License-Identifier: Apache-2.0
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if BOARD_ARDUINO_PORTENTA_C33
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config USE_DT_CODE_PARTITION
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default y
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if NETWORKING
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config NET_L2_ETHERNET
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default y
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config WIFI_ESP_HOSTED
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default y
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endif # NETWORKING
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endif # BOARD_ARDUINO_PORTENTA_C33
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/*
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* Copyright (c) 2025 Arduino SA
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/dt-bindings/gpio/arduino-mkr-header.h>
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/ {
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arduino_mkr_header: connector {
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compatible = "arduino-mkr-header";
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#gpio-cells = <2>;
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gpio-map-mask = <0xffffffff 0xffffffc0>;
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gpio-map-pass-thru = <0 0x3f>;
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gpio-map = <ARDUINO_MKR_HEADER_D0 0 &ioport1 5 0>, /* D0 */
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<ARDUINO_MKR_HEADER_D1 0 &ioport1 6 0>, /* D1 */
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<ARDUINO_MKR_HEADER_D2 0 &ioport1 11 0>, /* D2 */
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<ARDUINO_MKR_HEADER_D3 0 &ioport3 3 0>, /* D3 */
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<ARDUINO_MKR_HEADER_D4 0 &ioport4 1 0>, /* D4 */
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<ARDUINO_MKR_HEADER_D5 0 &ioport2 10 0>, /* D5 */
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<ARDUINO_MKR_HEADER_D6 0 &ioport6 1 0>, /* D6 */
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<ARDUINO_MKR_HEADER_D7 0 &ioport4 2 0>, /* D7 */
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<ARDUINO_MKR_HEADER_D8 0 &ioport9 0 0>, /* D8 / SPI_COPI */
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<ARDUINO_MKR_HEADER_D9 0 &ioport2 4 0>, /* D9 / SPI_SCK */
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<ARDUINO_MKR_HEADER_D10 0 &ioport3 15 0>, /* D10 / SPI_CIPO */
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<ARDUINO_MKR_HEADER_D11 0 &ioport4 7 0>, /* D11 / I2C_SDA */
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<ARDUINO_MKR_HEADER_D12 0 &ioport4 8 0>, /* D12 / I2C_SCL */
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<ARDUINO_MKR_HEADER_D13 0 &ioport1 10 0>, /* D13 / UART_RX */
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<ARDUINO_MKR_HEADER_D14 0 &ioport6 2 0>, /* D14 / UART_TX */
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<ARDUINO_MKR_HEADER_A0 0 &ioport0 6 0>, /* D15 / A0 */
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<ARDUINO_MKR_HEADER_A1 0 &ioport0 5 0>, /* D16 / A1 */
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<ARDUINO_MKR_HEADER_A2 0 &ioport0 4 0>, /* D17 / A2 */
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<ARDUINO_MKR_HEADER_A3 0 &ioport0 2 0>, /* D18 / A3 */
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<ARDUINO_MKR_HEADER_A4 0 &ioport0 1 0>, /* D19 / A4 */
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<ARDUINO_MKR_HEADER_A5 0 &ioport0 15 0>, /* D20 / A5 */
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<ARDUINO_MKR_HEADER_A6 0 &ioport0 14 0>; /* D21 / A6 */
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};
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};
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arduino_mkr_i2c: &iic0 {};
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arduino_mkr_serial: &uart9 {};
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/*
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* TODO: enable when SCI as SPI is supported
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* arduino_mkr_spi: &sci4 {};
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*/
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/*
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* Copyright (c) 2024 Arduino SA
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* SPDX-License-Identifier: Apache-2.0
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*/
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&pinctrl {
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sci7_default: sci7_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_7, 6, 13)>,
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<RA_PSEL(RA_PSEL_SCI_7, 6, 14)>,
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<RA_PSEL(RA_PSEL_SCI_7, 6, 11)>,
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<RA_PSEL(RA_PSEL_SCI_7, 4, 4)>;
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};
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};
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sci9_default: sci9_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_9, 6, 2)>,
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<RA_PSEL(RA_PSEL_SCI_9, 1, 10)>,
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<RA_PSEL(RA_PSEL_SCI_9, 6, 3)>,
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<RA_PSEL(RA_PSEL_SCI_9, 6, 4)>;
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};
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};
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sci5_default: sci5_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_5, 8, 5)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 13)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 8)>,
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<RA_PSEL(RA_PSEL_SCI_5, 5, 0)>;
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};
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};
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sci6_default: sci6_default {
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group1 {
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/* tx rx */
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psels = <RA_PSEL(RA_PSEL_SCI_6, 5, 6)>,
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<RA_PSEL(RA_PSEL_SCI_6, 3, 4)>,
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<RA_PSEL(RA_PSEL_SCI_6, 5, 3)>,
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<RA_PSEL(RA_PSEL_SCI_6, 5, 2)>;
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};
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};
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sci8_default: sci8_default {
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group1 {
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/* tx rx rts cts - BLE */
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psels = <RA_PSEL(RA_PSEL_SCI_8, 10, 0)>,
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<RA_PSEL(RA_PSEL_SCI_8, 6, 7)>,
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<RA_PSEL(RA_PSEL_SCI_8, 6, 6)>,
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<RA_PSEL(RA_PSEL_SCI_8, 8, 1)>;
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};
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};
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iic1_default: iic1_default {
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group1 {
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/* SCL1 SDA1 */
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psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>,
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<RA_PSEL(RA_PSEL_I2C, 5, 11)>;
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drive-strength = "medium";
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};
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};
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iic0_default: iic0_default {
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group1 {
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/* SCL SDA */
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psels = <RA_PSEL(RA_PSEL_I2C, 4, 8)>,
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<RA_PSEL(RA_PSEL_I2C, 4, 8)>;
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drive-strength = "medium";
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};
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};
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spi1_default: spi1_default {
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group1 {
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/* MISO MOSI RSPCK SSL0 SSL1 */
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psels = <RA_PSEL(RA_PSEL_SPI, 1, 0)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 1)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 2)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 3)>,
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<RA_PSEL(RA_PSEL_SPI, 1, 4)>;
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};
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};
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usbhs_default: usbhs_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_USBHS, 11, 1)>; /* USBHS-VBUS */
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drive-strength = "high";
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};
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};
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adc0_default: adc0_default {
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group1 {
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/* input */
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psels = <RA_PSEL(RA_PSEL_ADC, 0, 6)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 5)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 4)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 2)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 1)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 15)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 14)>,
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<RA_PSEL(RA_PSEL_ADC, 0, 0)>;
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renesas,analog-enable;
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};
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};
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ether_default: ether_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_ETH_RMII, 2, 14)>, /* ET0_MDC */
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<RA_PSEL(RA_PSEL_ETH_RMII, 2, 11)>, /* ET0_MDIO */
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<RA_PSEL(RA_PSEL_ETH_RMII, 4, 5)>, /* RMII0_TXD_EN_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */
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<RA_PSEL(RA_PSEL_ETH_RMII, 7, 5)>; /* RMII0_CRS_DV_B */
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drive-strength = "high";
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};
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};
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pwm1_default: pwm1_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 1, 5)>;
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};
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};
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pwm3_default: pwm3_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 1, 11)>;
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};
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};
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pwm4_default: pwm4_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 6, 8)>;
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};
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};
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pwm6_default: pwm6_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 6, 0)>,
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<RA_PSEL(RA_PSEL_GPT1, 6, 1)>;
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};
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};
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pwm7_default: pwm7_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 3, 3)>;
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};
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};
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pwm8_default: pwm8_default {
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group1 {
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psels = <RA_PSEL(RA_PSEL_GPT1, 1, 6)>,
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<RA_PSEL(RA_PSEL_GPT1, 6, 5)>;
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};
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};
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};

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