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| 1 | +/* |
| 2 | + * Copyright (c) 2024 Arduino SA |
| 3 | + * SPDX-License-Identifier: Apache-2.0 |
| 4 | + */ |
| 5 | + |
| 6 | +&pinctrl { |
| 7 | + sci7_default: sci7_default { |
| 8 | + group1 { |
| 9 | + /* tx rx */ |
| 10 | + psels = <RA_PSEL(RA_PSEL_SCI_7, 6, 13)>, |
| 11 | + <RA_PSEL(RA_PSEL_SCI_7, 6, 14)>, |
| 12 | + <RA_PSEL(RA_PSEL_SCI_7, 6, 11)>, |
| 13 | + <RA_PSEL(RA_PSEL_SCI_7, 4, 4)>; |
| 14 | + }; |
| 15 | + }; |
| 16 | + |
| 17 | + sci9_default: sci9_default { |
| 18 | + group1 { |
| 19 | + /* tx rx */ |
| 20 | + psels = <RA_PSEL(RA_PSEL_SCI_9, 6, 2)>, |
| 21 | + <RA_PSEL(RA_PSEL_SCI_9, 1, 10)>, |
| 22 | + <RA_PSEL(RA_PSEL_SCI_9, 6, 3)>, |
| 23 | + <RA_PSEL(RA_PSEL_SCI_9, 6, 4)>; |
| 24 | + }; |
| 25 | + }; |
| 26 | + |
| 27 | + sci5_default: sci5_default { |
| 28 | + group1 { |
| 29 | + /* tx rx */ |
| 30 | + psels = <RA_PSEL(RA_PSEL_SCI_5, 8, 5)>, |
| 31 | + <RA_PSEL(RA_PSEL_SCI_5, 5, 13)>, |
| 32 | + <RA_PSEL(RA_PSEL_SCI_5, 5, 8)>, |
| 33 | + <RA_PSEL(RA_PSEL_SCI_5, 5, 0)>; |
| 34 | + }; |
| 35 | + }; |
| 36 | + |
| 37 | + sci6_default: sci6_default { |
| 38 | + group1 { |
| 39 | + /* tx rx */ |
| 40 | + psels = <RA_PSEL(RA_PSEL_SCI_6, 5, 6)>, |
| 41 | + <RA_PSEL(RA_PSEL_SCI_6, 3, 4)>, |
| 42 | + <RA_PSEL(RA_PSEL_SCI_6, 5, 3)>, |
| 43 | + <RA_PSEL(RA_PSEL_SCI_6, 5, 2)>; |
| 44 | + }; |
| 45 | + }; |
| 46 | + |
| 47 | + sci8_default: sci8_default { |
| 48 | + group1 { |
| 49 | + /* tx rx rts cts - BLE */ |
| 50 | + psels = <RA_PSEL(RA_PSEL_SCI_8, 10, 0)>, |
| 51 | + <RA_PSEL(RA_PSEL_SCI_8, 6, 7)>, |
| 52 | + <RA_PSEL(RA_PSEL_SCI_8, 6, 6)>, |
| 53 | + <RA_PSEL(RA_PSEL_SCI_8, 8, 1)>; |
| 54 | + }; |
| 55 | + }; |
| 56 | + |
| 57 | + iic1_default: iic1_default { |
| 58 | + group1 { |
| 59 | + /* SCL1 SDA1 */ |
| 60 | + psels = <RA_PSEL(RA_PSEL_I2C, 5, 12)>, |
| 61 | + <RA_PSEL(RA_PSEL_I2C, 5, 11)>; |
| 62 | + drive-strength = "medium"; |
| 63 | + }; |
| 64 | + }; |
| 65 | + |
| 66 | + iic0_default: iic0_default { |
| 67 | + group1 { |
| 68 | + /* SCL SDA */ |
| 69 | + psels = <RA_PSEL(RA_PSEL_I2C, 4, 8)>, |
| 70 | + <RA_PSEL(RA_PSEL_I2C, 4, 8)>; |
| 71 | + drive-strength = "medium"; |
| 72 | + }; |
| 73 | + }; |
| 74 | + |
| 75 | + spi1_default: spi1_default { |
| 76 | + group1 { |
| 77 | + /* MISO MOSI RSPCK SSL0 SSL1 */ |
| 78 | + psels = <RA_PSEL(RA_PSEL_SPI, 1, 0)>, |
| 79 | + <RA_PSEL(RA_PSEL_SPI, 1, 1)>, |
| 80 | + <RA_PSEL(RA_PSEL_SPI, 1, 2)>, |
| 81 | + <RA_PSEL(RA_PSEL_SPI, 1, 3)>, |
| 82 | + <RA_PSEL(RA_PSEL_SPI, 1, 4)>; |
| 83 | + }; |
| 84 | + }; |
| 85 | + |
| 86 | + usbhs_default: usbhs_default { |
| 87 | + group1 { |
| 88 | + psels = <RA_PSEL(RA_PSEL_USBHS, 11, 1)>; /* USBHS-VBUS */ |
| 89 | + drive-strength = "high"; |
| 90 | + }; |
| 91 | + }; |
| 92 | + |
| 93 | + adc0_default: adc0_default { |
| 94 | + group1 { |
| 95 | + /* input */ |
| 96 | + psels = <RA_PSEL(RA_PSEL_ADC, 0, 6)>, |
| 97 | + <RA_PSEL(RA_PSEL_ADC, 0, 5)>, |
| 98 | + <RA_PSEL(RA_PSEL_ADC, 0, 4)>, |
| 99 | + <RA_PSEL(RA_PSEL_ADC, 0, 2)>, |
| 100 | + <RA_PSEL(RA_PSEL_ADC, 0, 1)>, |
| 101 | + <RA_PSEL(RA_PSEL_ADC, 0, 15)>, |
| 102 | + <RA_PSEL(RA_PSEL_ADC, 0, 14)>, |
| 103 | + <RA_PSEL(RA_PSEL_ADC, 0, 0)>; |
| 104 | + renesas,analog-enable; |
| 105 | + }; |
| 106 | + }; |
| 107 | + |
| 108 | + ether_default: ether_default { |
| 109 | + group1 { |
| 110 | + psels = <RA_PSEL(RA_PSEL_ETH_RMII, 2, 14)>, /* ET0_MDC */ |
| 111 | + <RA_PSEL(RA_PSEL_ETH_RMII, 2, 11)>, /* ET0_MDIO */ |
| 112 | + <RA_PSEL(RA_PSEL_ETH_RMII, 4, 5)>, /* RMII0_TXD_EN_B */ |
| 113 | + <RA_PSEL(RA_PSEL_ETH_RMII, 4, 6)>, /* RMII0_TXD1_BR */ |
| 114 | + <RA_PSEL(RA_PSEL_ETH_RMII, 7, 0)>, /* RMII0_TXD0_B */ |
| 115 | + <RA_PSEL(RA_PSEL_ETH_RMII, 7, 1)>, /* REF50CK0_B */ |
| 116 | + <RA_PSEL(RA_PSEL_ETH_RMII, 7, 2)>, /* RMII0_RXD0_B */ |
| 117 | + <RA_PSEL(RA_PSEL_ETH_RMII, 7, 3)>, /* RMII0_RXD1_B */ |
| 118 | + <RA_PSEL(RA_PSEL_ETH_RMII, 7, 4)>, /* RMII0_RX_ER_B */ |
| 119 | + <RA_PSEL(RA_PSEL_ETH_RMII, 7, 5)>; /* RMII0_CRS_DV_B */ |
| 120 | + drive-strength = "high"; |
| 121 | + }; |
| 122 | + }; |
| 123 | + |
| 124 | + pwm1_default: pwm1_default { |
| 125 | + group1 { |
| 126 | + psels = <RA_PSEL(RA_PSEL_GPT1, 1, 5)>; |
| 127 | + }; |
| 128 | + }; |
| 129 | + |
| 130 | + pwm3_default: pwm3_default { |
| 131 | + group1 { |
| 132 | + psels = <RA_PSEL(RA_PSEL_GPT1, 1, 11)>; |
| 133 | + }; |
| 134 | + }; |
| 135 | + |
| 136 | + pwm4_default: pwm4_default { |
| 137 | + group1 { |
| 138 | + psels = <RA_PSEL(RA_PSEL_GPT1, 6, 8)>; |
| 139 | + }; |
| 140 | + }; |
| 141 | + |
| 142 | + pwm6_default: pwm6_default { |
| 143 | + group1 { |
| 144 | + psels = <RA_PSEL(RA_PSEL_GPT1, 6, 0)>, |
| 145 | + <RA_PSEL(RA_PSEL_GPT1, 6, 1)>; |
| 146 | + }; |
| 147 | + }; |
| 148 | + |
| 149 | + pwm7_default: pwm7_default { |
| 150 | + group1 { |
| 151 | + psels = <RA_PSEL(RA_PSEL_GPT1, 3, 3)>; |
| 152 | + }; |
| 153 | + }; |
| 154 | + |
| 155 | + pwm8_default: pwm8_default { |
| 156 | + group1 { |
| 157 | + psels = <RA_PSEL(RA_PSEL_GPT1, 1, 6)>, |
| 158 | + <RA_PSEL(RA_PSEL_GPT1, 6, 5)>; |
| 159 | + }; |
| 160 | + }; |
| 161 | +}; |
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