@@ -125,6 +125,32 @@ static status_t is_area_readable(uint32_t addr, size_t len)
125125}
126126#endif /* CONFIG_CHECK_BEFORE_READING && ! CONFIG_SOC_LPC55S36 */
127127
128+ #define SOC_FLASH_NEED_CLEAR_CACHES 1
129+ #ifdef CONFIG_SOC_SERIES_MCXW
130+ static void clear_flash_caches (void )
131+ {
132+ volatile uint32_t * const smscm_ocmdr0 = (volatile uint32_t * )0x40015400 ;
133+ /* this bit clears the flash cache */
134+ * smscm_ocmdr0 |= BIT (8 );
135+ volatile uint32_t * mcm_cpcr2 = (volatile uint32_t * )0xe0080034 ;
136+ /* this bit clears the code cache */
137+ * mcm_cpcr2 |= BIT (0 );
138+ }
139+ #elif CONFIG_SOC_SERIES_MCXN
140+ static void clear_flash_caches (void )
141+ {
142+ volatile uint32_t * const nvm_ctrl = (volatile uint32_t * )0x40000400 ;
143+ /* this bit clears the flash cache */
144+ * nvm_ctrl |= BIT (5 );
145+ volatile uint32_t * const lpcac_ctrl = (volatile uint32_t * )0x40000824 ;
146+ /* this bit clears the code cache */
147+ * lpcac_ctrl |= BIT (1 );
148+ }
149+ #else
150+ #undef SOC_FLASH_NEED_CLEAR_CACHES
151+ #define clear_flash_caches (...)
152+ #endif
153+
128154struct flash_priv {
129155 flash_config_t config ;
130156 /*
@@ -172,6 +198,11 @@ static int flash_mcux_erase(const struct device *dev, off_t offset,
172198 (FMU_Type * ) DT_INST_REG_ADDR (0 ),
173199#endif
174200 addr , len , kFLASH_ApiEraseKey );
201+
202+ if (IS_ENABLED (SOC_FLASH_NEED_CLEAR_CACHES )) {
203+ clear_flash_caches ();
204+ }
205+
175206 irq_unlock (key );
176207
177208 k_sem_give (& priv -> write_lock );
@@ -277,6 +308,11 @@ static int flash_mcux_write(const struct device *dev, off_t offset,
277308 (FMU_Type * ) DT_INST_REG_ADDR (0 ),
278309#endif
279310 addr , (uint8_t * ) data , len );
311+
312+ if (IS_ENABLED (SOC_FLASH_NEED_CLEAR_CACHES )) {
313+ clear_flash_caches ();
314+ }
315+
280316 irq_unlock (key );
281317
282318 k_sem_give (& priv -> write_lock );
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