dts: gd32e1: change gd32 pinctrl

feilongfl · feilongfl · commit e9fa65fad1e8 · 2021-09-19T05:45:10.000+08:00
change gd32 pinctrl

Signed-off-by: YuLong Yao &lt;feilongphone@gmail.com&gt;
diff --git a/boards/arm/gd32e103v_eval/gd32e103v_eval.dts b/boards/arm/gd32e103v_eval/gd32e103v_eval.dts
@@ -8,7 +8,7 @@
 /dts-v1/;
 
 #include <gigadevice/e1/gd32e103Xb.dtsi>
-#include <gd/e1/gd32e103c(b-c-e)tx-pinctrl.dtsi>
+#include <gd/e1/gd32e103v(8-b)tx-pinctrl.dtsi>
 
 / {
 	model = "GigaDevice GD32E103VB-EVAL board";
diff --git a/dts/arm/gigadevice/e1/gd32e1.dtsi b/dts/arm/gigadevice/e1/gd32e1.dtsi
@@ -144,11 +144,11 @@
 			reg = <0x40010400 0x400>;
 		};
 
-		pinctrl: pin-controller@40010000 {
+		pinctrl: pin-controller@40010800 {
 			compatible = "gd,gd32-pinctrl";
 			#address-cells = <1>;
 			#size-cells = <1>;
-			reg = <0x40010000 0x2000>;
+			reg = <0x40010800 0x2000>;
 
 			gpioa: gpio@40010800 {
 				compatible = "gd,gd32-gpio";
diff --git a/dts/bindings/pinctrl/gd,gd32-pinctrl.yaml b/dts/bindings/pinctrl/gd,gd32-pinctrl.yaml
@@ -1,76 +1,104 @@
 # Copyright (c) 2020 Linaro Limited
 # SPDX-License-Identifier: Apache-2.0
 
-description: |
-    GD32 Pin controller Node
-    Based on pincfg-node.yaml binding.
-
-    Note: `bias-disable` and `drive-push-pull` are default pin configurations.
-           They will be applied in case no `bias-foo` or `driver-bar` properties
-           are set.
+description: GD32 Pin controller Node
 
 compatible: "gd,gd32-pinctrl"
 
-include:
-    - name: base.yaml
-    - name: pincfg-node.yaml
-      child-binding:
-        property-allowlist:
-          - bias-disable
-          - bias-pull-down
-          - bias-pull-up
-          - drive-push-pull
-          - drive-open-drain
+include: [base.yaml]
 
 properties:
     reg:
       required: true
 
 child-binding:
     description: |
-        This binding gives a base representation of the STM32 pins configration
+        This binding gives a base representation of the GD32F1 pins
+        configration
 
     properties:
         pinmux:
           required: true
           type: int
           description: |
-            Reused from https://github.com/torvalds/linux/blob/master/Documentation/devicetree/bindings/pinctrl/st,stm32-pinctrl.yaml
             Integer array, represents gpio pin number and mux setting.
-            These defines are calculated as: ((port * 16 + line) << 8) | function
+            These defines are calculated as: ((port * 16 + line) << 8) | (function << 6) | remap)
             With:
             - port: The gpio port index (PA = 0, PB = 1, ..., PK = 11)
             - line: The line offset within the port (PA0 = 0, PA1 = 1, ..., PA15 = 15)
-            - function: The function number, can be:
-            * 0 : Alternate Function 0
-            * 1 : Alternate Function 1
-            * 2 : Alternate Function 2
-            * ...
-            * 15 : Alternate Function 15
-            * 16 : Analog
+            - function: The configuration mode, can be:
+            * 0 : Alternate function output
+            * 1 : Input
+            * 2 : Analog
+            - remap: The pin remapping configuration. It allows to assign the pin
+            function to a different peripheral. Remain configuration can be:
+            * 0 : No remap
+            * 1 : Partial remap 1
+            * 2 : Partial remap 2
+            * 3 : Partial remap 3
+            * 4 : Full remap
             To simplify the usage, macro is available to generate "pinmux" field.
             This macro is available here:
-              -include/dt-bindings/pinctrl/stm32-pinctrl-common.h
+              -include/dt-bindings/pinctrl/gd32-pinctrl.h
             Some examples of macro usage:
-               GPIO A9 set as alernate function 2
+               GPIO A9 set as alernate with no remap
+            ... {
+                     pinmux = <GD32F1_PINMUX('A', 9, ALTERNATE, REMAP_NO)>;
+            };
+               GPIO A9 set as alernate with full remap
             ... {
-                     pinmux = <STM32_PINMUX('A', 9, AF2)>;
+                     pinmux = <GD32F1_PINMUX('A', 9, ALTERNATE, REMAP_FULL)>;
             };
-               GPIO A9 set as analog
+               GPIO A9 set as input
             ... {
-                     pinmux = <STM32_PINMUX('A', 9, ANALOG)>;
+                     pinmux = <GD32F1_PINMUX('A', 9, GPIO_IN, REMAP_NO)>;
             };
 
+        bias-disable:
+          required: false
+          type: boolean
+          description: |
+            Pin bias (push-pull) disabled. This is the default pin
+            configuration and will be applied if no bias- property is
+            specified. Only available in input mode ("floating" configuration).
+
+        bias-pull-down:
+          required: false
+          type: boolean
+          description: |
+            Weak pull down resistor enabled. Not compatible with
+            output configuration modes (atlernate or general purpose output).
+
+        bias-pull-up:
+          required: false
+          type: boolean
+          description: |
+            Weak pull up resistor enabled. Not compatible with
+            output configuration modes (atlernate or general purpose output).
+
+        drive-push-pull:
+          required: false
+          type: boolean
+          description: |
+            Pin driven actively high and low. This is the default pin
+            configueration and will be applied if no drive- property is
+            specified. Only valid for output configuration modes.
+
+        drive-open-drain:
+          required: false
+          type: boolean
+          description: |
+            Pin driven in open drain. Only valid for output
+            configuration modes.
+
         slew-rate:
           required: false
           type: string
-          default: "low-speed"
+          default: "max-speed-10mhz"
           enum:
-          - "low-speed"           # Default value.
-          - "medium-speed"
-          - "high-speed"
-          - "very-high-speed"
+          - "max-speed-10mhz"       # Default
+          - "max-speed-2mhz"
+          - "max-speed-50mhz"
           description: |
-            Pin speed. Default to low-speed. For few pins (PA11 and
-            PB3 depending on SoCs)hardware reset value could differ
-            (very-high-speed). Carefully check reference manual for these pins.
+            Pin output mode, maximum achievable speed. Only applies to
+            output mode (alternate).
diff --git a/include/dt-bindings/pinctrl/gd32-pinctrl.h b/include/dt-bindings/pinctrl/gd32-pinctrl.h
@@ -223,4 +223,134 @@
 #define GD32_PIN_PK14  GD32PIN(GD32_PORTK, 14)
 #define GD32_PIN_PK15  GD32PIN(GD32_PORTK, 15)
 
+/**
+ * @brief Macro to generate pinmux int using port, pin number and mode arguments
+ */
+
+#define PIN_NO(port, line)	(((port) - 'A') * 0x10 + (line))
+#define GD32_PINMUX(port, line, mode, remap) \
+			(((PIN_NO(port, line)) << 8) | (mode << 6) | (remap))
+
+/**
+ * @brief Pin modes
+ */
+
+#define ALTERNATE	0x0  /* Alternate function output */
+#define GPIO_IN		0x1  /* Input */
+#define ANALOG		0x2  /* Analog */
+
+/**
+ * @brief Pin remapping configurations
+ */
+
+#define NO_REMAP	0x0  /* No remapping */
+#define REMAP_1		0x1  /* Partial remapping 1 */
+#define REMAP_2		0x2  /* Partial remapping 2 */
+#define REMAP_3		0x3  /* Partial remapping 3 */
+#define REMAP_FULL	0x4  /* Full remapping */
+
+/**
+ * @brief PIN configuration bitfield
+ *
+ * Pin configuration is coded with the following
+ * fields
+ *    GPIO I/O Mode       [ 0 ]
+ *    GPIO Input config   [ 1 : 2 ]
+ *    GPIO Output speed   [ 3 : 4 ]
+ *    GPIO Output PP/OD   [ 5 ]
+ *    GPIO Output AF/GP   [ 6 ]
+ *    GPIO PUPD Config    [ 7 : 8 ]
+ *
+ * Applicable to GD32F1 series
+ */
+
+/* Alternate functions */
+/* GD32F1 Pinmux doesn't use explicit alternate functions */
+/* These are kept for compatibility with other GD32 pinmux */
+#define GD32_AFR_MASK			0
+#define GD32_AFR_SHIFT			0
+
+/* Port Mode */
+#define GD32_MODE_INPUT		(0x0<<GD32_MODE_INOUT_SHIFT)
+#define GD32_MODE_OUTPUT		(0x1<<GD32_MODE_INOUT_SHIFT)
+#define GD32_MODE_INOUT_MASK		0x1
+#define GD32_MODE_INOUT_SHIFT		0
+
+/* Input Port configuration */
+#define GD32_CNF_IN_ANALOG		(0x0<<GD32_CNF_IN_SHIFT)
+#define GD32_CNF_IN_FLOAT		(0x1<<GD32_CNF_IN_SHIFT)
+#define GD32_CNF_IN_PUPD		(0x2<<GD32_CNF_IN_SHIFT)
+#define GD32_CNF_IN_MASK		0x3
+#define GD32_CNF_IN_SHIFT		1
+
+/* Output Port configuration */
+#define GD32_MODE_OUTPUT_MAX_10	(0x0<<GD32_MODE_OSPEED_SHIFT)
+#define GD32_MODE_OUTPUT_MAX_2		(0x1<<GD32_MODE_OSPEED_SHIFT)
+#define GD32_MODE_OUTPUT_MAX_50	(0x2<<GD32_MODE_OSPEED_SHIFT)
+#define GD32_MODE_OSPEED_MASK		0x3
+#define GD32_MODE_OSPEED_SHIFT		3
+
+#define GD32_CNF_PUSH_PULL		(0x0<<GD32_CNF_OUT_0_SHIFT)
+#define GD32_CNF_OPEN_DRAIN		(0x1<<GD32_CNF_OUT_0_SHIFT)
+#define GD32_CNF_OUT_0_MASK		0x1
+#define GD32_CNF_OUT_0_SHIFT		5
+
+#define GD32_CNF_GP_OUTPUT		(0x0<<GD32_CNF_OUT_1_SHIFT)
+#define GD32_CNF_ALT_FUNC		(0x1<<GD32_CNF_OUT_1_SHIFT)
+#define GD32_CNF_OUT_1_MASK		0x1
+#define GD32_CNF_OUT_1_SHIFT		6
+
+/* GPIO High impedance/Pull-up/Pull-down */
+#define GD32_PUPD_NO_PULL		(0x0<<GD32_PUPD_SHIFT)
+#define GD32_PUPD_PULL_UP		(0x1<<GD32_PUPD_SHIFT)
+#define GD32_PUPD_PULL_DOWN		(0x2<<GD32_PUPD_SHIFT)
+#define GD32_PUPD_MASK			0x3
+#define GD32_PUPD_SHIFT		7
+
+/* Alternate defines */
+/* IO pin functions are mostly common across GD32 devices. Notable
+ * exception is GD32F1 as these MCUs do not have registers for
+ * configuration of pin's alternate function. The configuration is
+ * done implicitly by setting specific mode and config in MODE and CNF
+ * registers for particular pin.
+ */
+#define GD32_ALTERNATE			(GD32_MODE_OUTPUT | GD32_CNF_ALT_FUNC)
+
+#define GD32_PIN_USART_TX		(GD32_ALTERNATE | GD32_CNF_PUSH_PULL)
+#define GD32_PIN_USART_RX		(GD32_MODE_INPUT | GD32_CNF_IN_FLOAT)
+#define GD32_PIN_I2C			(GD32_ALTERNATE | GD32_CNF_OPEN_DRAIN)
+#define GD32_PIN_PWM			(GD32_ALTERNATE | GD32_CNF_PUSH_PULL)
+#define GD32_PIN_SPI_MASTER_SCK	(GD32_ALTERNATE | GD32_CNF_PUSH_PULL)
+#define GD32_PIN_SPI_SLAVE_SCK		(GD32_MODE_INPUT | GD32_CNF_IN_FLOAT)
+#define GD32_PIN_SPI_MASTER_MOSI	(GD32_ALTERNATE | GD32_CNF_PUSH_PULL)
+#define GD32_PIN_SPI_SLAVE_MOSI	(GD32_MODE_INPUT | GD32_CNF_IN_FLOAT)
+#define GD32_PIN_SPI_MASTER_MISO	(GD32_MODE_INPUT | GD32_CNF_IN_FLOAT)
+#define GD32_PIN_SPI_SLAVE_MISO	(GD32_ALTERNATE | GD32_CNF_PUSH_PULL)
+#define GD32_PIN_CAN_TX		(GD32_ALTERNATE | GD32_CNF_PUSH_PULL)
+#define GD32_PIN_CAN_RX		(GD32_MODE_INPUT  | GD32_PUPD_PULL_UP)
+
+/*
+ * Reference manual (RM0008)
+ * Section 25.3.1: Slave select (NSS) pin management
+ *
+ * Hardware NSS management:
+ * - NSS output disabled: allows multimaster capability for devices operating
+ *   in master mode.
+ * - NSS output enabled: used only when the device operates in master mode.
+ *
+ * Software NSS management:
+ * - External NSS pin remains free for other application uses.
+ *
+ */
+
+/* Hardware master NSS output disabled */
+#define GD32_PIN_SPI_MASTER_NSS	(GD32_MODE_INPUT | GD32_CNF_IN_FLOAT)
+/* Hardware master NSS output enabled */
+#define GD32_PIN_SPI_MASTER_NSS_OE	(GD32_MODE_OUTPUT | \
+						GD32_CNF_ALT_FUNC | \
+						GD32_CNF_PUSH_PULL)
+#define GD32_PIN_SPI_SLAVE_NSS		(GD32_MODE_INPUT | GD32_CNF_IN_FLOAT)
+#define GD32_PIN_USB			(GD32_MODE_INPUT | GD32_CNF_IN_PUPD)
+
+
 #endif	/* ZEPHYR_GD32_PINCTRL_COMMON_H_ */
diff --git a/west.yml b/west.yml
@@ -137,7 +137,7 @@ manifest:
         - hal
     - name: hal_gd32
       remote: feilongfl_temp
-      revision: 3b4c2f7fdf8e67387e43f5939bb829a52ad2a575
+      revision: c8c63a71d8eed34dd896580aab01617f43e45a6e
       path: modules/hal/gigadevice
     - name: libmetal
       revision: 39d049d4ae68e6f6d595fce7de1dcfc1024fb4eb
