1616#include <zephyr/logging/log.h>
1717LOG_MODULE_DECLARE (LIS2DUX12_RTIO );
1818
19- /*
20- * Create a chain of SQEs representing a bus transaction to read a reg.
21- * The RTIO-enabled bus driver will:
22- *
23- * - write "reg" address
24- * - read "len" data bytes into "buf".
25- * - call complete_op callback
26- *
27- * If drdy_xl is active it reads XL data (6 bytes) from LIS2DUX12_OUTX_L_A reg.
28- */
29- static void lis2dux12_rtio_rw_transaction (const struct device * dev , uint8_t reg ,
30- uint8_t * buf , uint32_t len ,
31- rtio_callback_t complete_op_cb )
32- {
33- struct lis2dux12_data * lis2dux12 = dev -> data ;
34- struct rtio * rtio = lis2dux12 -> rtio_ctx ;
35- struct rtio_iodev * iodev = lis2dux12 -> iodev ;
36- struct rtio_sqe * write_addr = rtio_sqe_acquire (rtio );
37- struct rtio_sqe * read_reg = rtio_sqe_acquire (rtio );
38- struct rtio_sqe * complete_op = rtio_sqe_acquire (rtio );
39- struct rtio_iodev_sqe * sqe = lis2dux12 -> streaming_sqe ;
40- uint8_t reg_bus = lis2dux12_bus_reg (lis2dux12 , reg );
41-
42- /* check we have been able to acquire sqe */
43- if (write_addr == NULL || read_reg == NULL || complete_op == NULL ) {
44- return ;
45- }
46-
47- rtio_sqe_prep_tiny_write (write_addr , iodev , RTIO_PRIO_NORM , & reg_bus , 1 , NULL );
48- write_addr -> flags = RTIO_SQE_TRANSACTION ;
49- rtio_sqe_prep_read (read_reg , iodev , RTIO_PRIO_NORM , buf , len , NULL );
50- read_reg -> flags = RTIO_SQE_CHAINED ;
51- if (lis2dux12 -> bus_type == BUS_I2C ) {
52- read_reg -> iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART ;
53- }
54-
55- rtio_sqe_prep_callback_no_cqe (complete_op , complete_op_cb , (void * )dev , sqe );
56- rtio_submit (rtio , 0 );
57- }
58-
5919void lis2dux12_submit_stream (const struct device * dev , struct rtio_iodev_sqe * iodev_sqe )
6020{
6121 struct lis2dux12_data * lis2dux12 = dev -> data ;
@@ -180,19 +140,9 @@ static void lis2dux12_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe,
180140 }
181141
182142 /* flush completion */
183- struct rtio_cqe * cqe ;
184143 int res = 0 ;
185144
186- do {
187- cqe = rtio_cqe_consume (rtio );
188- if (cqe != NULL ) {
189- if ((cqe -> result < 0 ) && (res == 0 )) {
190- LOG_ERR ("Bus error: %d" , cqe -> result );
191- res = cqe -> result ;
192- }
193- rtio_cqe_release (rtio , cqe );
194- }
195- } while (cqe != NULL );
145+ res = rtio_flush_completion_queue (rtio );
196146
197147 /* Bail/cancel attempt to read sensor on any error */
198148 if (res != 0 ) {
@@ -299,6 +249,19 @@ static void lis2dux12_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe,
299249 read_buf = buf + sizeof (hdr );
300250 buf_avail = buf_len - sizeof (hdr );
301251
252+ uint8_t reg_addr = lis2dux12_bus_reg (lis2dux12 -> bus_type , LIS2DUXXX_DT_FIFO_DATA_OUT_TAG );
253+ struct rtio_regs fifo_regs ;
254+ struct rtio_regs_list regs_list [] = {
255+ {
256+ reg_addr ,
257+ read_buf ,
258+ buf_avail ,
259+ },
260+ };
261+
262+ fifo_regs .rtio_regs_list = regs_list ;
263+ fifo_regs .rtio_regs_num = ARRAY_SIZE (regs_list );
264+
302265 /*
303266 * Prepare rtio enabled bus to read all fifo_count entries from
304267 * LIS2DUX12_FIFO_DATA_OUT_TAG. Then lis2dux12_complete_op_cb
@@ -314,8 +277,8 @@ static void lis2dux12_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe,
314277 * lis2dux12_fifo_out_raw_get(&dev_ctx, &f_data);
315278 * }
316279 */
317- lis2dux12_rtio_rw_transaction ( dev , LIS2DUXXX_DT_FIFO_DATA_OUT_TAG ,
318- read_buf , buf_avail , lis2dux12_complete_op_cb );
280+ rtio_read_regs_async ( lis2dux12 -> rtio_ctx , lis2dux12 -> iodev , lis2dux12 -> bus_type ,
281+ & fifo_regs , lis2dux12 -> streaming_sqe , dev , lis2dux12_complete_op_cb );
319282}
320283
321284/*
@@ -351,19 +314,9 @@ static void lis2dux12_read_status_cb(struct rtio *r, const struct rtio_sqe *sqe,
351314 }
352315
353316 /* flush completion */
354- struct rtio_cqe * cqe ;
355317 int res = 0 ;
356318
357- do {
358- cqe = rtio_cqe_consume (rtio );
359- if (cqe != NULL ) {
360- if ((cqe -> result < 0 ) && (res == 0 )) {
361- LOG_ERR ("Bus error: %d" , cqe -> result );
362- res = cqe -> result ;
363- }
364- rtio_cqe_release (rtio , cqe );
365- }
366- } while (cqe != NULL );
319+ res = rtio_flush_completion_queue (rtio );
367320
368321 /* Bail/cancel attempt to read sensor on any error */
369322 if (res != 0 ) {
@@ -439,6 +392,19 @@ static void lis2dux12_read_status_cb(struct rtio *r, const struct rtio_sqe *sqe,
439392 memcpy (buf , & hdr , sizeof (hdr ));
440393 read_buf = (uint8_t * )& ((struct lis2dux12_rtio_data * )buf )-> acc [0 ];
441394
395+ uint8_t reg_addr = lis2dux12_bus_reg (lis2dux12 -> bus_type , LIS2DUXXX_DT_OUTX_L );
396+ struct rtio_regs fifo_regs ;
397+ struct rtio_regs_list regs_list [] = {
398+ {
399+ reg_addr ,
400+ read_buf ,
401+ 6 ,
402+ },
403+ };
404+
405+ fifo_regs .rtio_regs_list = regs_list ;
406+ fifo_regs .rtio_regs_num = ARRAY_SIZE (regs_list );
407+
442408 /*
443409 * Prepare rtio enabled bus to read LIS2DUX12_OUTX_L_A register
444410 * where accelerometer data is available.
@@ -450,8 +416,9 @@ static void lis2dux12_read_status_cb(struct rtio *r, const struct rtio_sqe *sqe,
450416 *
451417 * lis2dux12_acceleration_raw_get(&dev_ctx, accel_raw);
452418 */
453- lis2dux12_rtio_rw_transaction (dev , LIS2DUXXX_DT_OUTX_L ,
454- read_buf , 6 , lis2dux12_complete_op_cb );
419+ rtio_read_regs_async (lis2dux12 -> rtio_ctx , lis2dux12 -> iodev , lis2dux12 -> bus_type ,
420+ & fifo_regs , lis2dux12 -> streaming_sqe , dev ,
421+ lis2dux12_complete_op_cb );
455422 }
456423}
457424
@@ -486,6 +453,20 @@ void lis2dux12_stream_irq_handler(const struct device *dev)
486453 if (lis2dux12 -> trig_cfg .int_fifo_th || lis2dux12 -> trig_cfg .int_fifo_full ) {
487454 lis2dux12 -> fifo_status [0 ] = lis2dux12 -> fifo_status [1 ] = 0 ;
488455
456+ uint8_t reg_addr =
457+ lis2dux12_bus_reg (lis2dux12 -> bus_type , LIS2DUXXX_DT_FIFO_STATUS1 );
458+ struct rtio_regs fifo_regs ;
459+ struct rtio_regs_list regs_list [] = {
460+ {
461+ reg_addr ,
462+ lis2dux12 -> fifo_status ,
463+ 2 ,
464+ },
465+ };
466+
467+ fifo_regs .rtio_regs_list = regs_list ;
468+ fifo_regs .rtio_regs_num = ARRAY_SIZE (regs_list );
469+
489470 /*
490471 * Prepare rtio enabled bus to read LIS2DUX12_FIFO_STATUS1 and
491472 * LIS2DUX12_FIFO_STATUS2 registers where FIFO threshold condition and
@@ -500,14 +481,29 @@ void lis2dux12_stream_irq_handler(const struct device *dev)
500481 * uint16_t num;
501482 * lis2duxs12_fifo_data_level_get(&dev_ctx, &num);
502483 */
503- lis2dux12_rtio_rw_transaction (dev , LIS2DUXXX_DT_FIFO_STATUS1 ,
504- lis2dux12 -> fifo_status , 2 , lis2dux12_read_fifo_cb );
484+ rtio_read_regs_async (lis2dux12 -> rtio_ctx , lis2dux12 -> iodev ,
485+ lis2dux12 -> bus_type , & fifo_regs ,
486+ lis2dux12 -> streaming_sqe , dev ,
487+ lis2dux12_read_fifo_cb );
505488 }
506489
507490 /* handle drdy trigger */
508491 if (lis2dux12 -> trig_cfg .int_drdy ) {
509492 lis2dux12 -> status = 0 ;
510493
494+ uint8_t reg_addr = lis2dux12_bus_reg (lis2dux12 -> bus_type , LIS2DUXXX_DT_STATUS );
495+ struct rtio_regs fifo_regs ;
496+ struct rtio_regs_list regs_list [] = {
497+ {
498+ reg_addr ,
499+ & lis2dux12 -> status ,
500+ 1 ,
501+ },
502+ };
503+
504+ fifo_regs .rtio_regs_list = regs_list ;
505+ fifo_regs .rtio_regs_num = ARRAY_SIZE (regs_list );
506+
511507 /*
512508 * Prepare rtio enabled bus to read LIS2DUX12_STATUS_REG register
513509 * where accelerometer and gyroscope data ready status is available.
@@ -519,7 +515,8 @@ void lis2dux12_stream_irq_handler(const struct device *dev)
519515 *
520516 * lis2dux12_flag_data_ready_get(&dev_ctx, &drdy);
521517 */
522- lis2dux12_rtio_rw_transaction (dev , LIS2DUXXX_DT_STATUS ,
523- & lis2dux12 -> status , 1 , lis2dux12_read_status_cb );
518+ rtio_read_regs_async (lis2dux12 -> rtio_ctx , lis2dux12 -> iodev , lis2dux12 -> bus_type ,
519+ & fifo_regs , lis2dux12 -> streaming_sqe , dev ,
520+ lis2dux12_read_status_cb );
524521 }
525522}
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