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#include <zephyr/logging/log.h>
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LOG_MODULE_DECLARE (LIS2DUX12_RTIO );
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- /*
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- * Create a chain of SQEs representing a bus transaction to read a reg.
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- * The RTIO-enabled bus driver will:
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- *
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- * - write "reg" address
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- * - read "len" data bytes into "buf".
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- * - call complete_op callback
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- *
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- * If drdy_xl is active it reads XL data (6 bytes) from LIS2DUX12_OUTX_L_A reg.
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- */
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- static void lis2dux12_rtio_rw_transaction (const struct device * dev , uint8_t reg ,
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- uint8_t * buf , uint32_t len ,
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- rtio_callback_t complete_op_cb )
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- {
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- struct lis2dux12_data * lis2dux12 = dev -> data ;
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- struct rtio * rtio = lis2dux12 -> rtio_ctx ;
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- struct rtio_iodev * iodev = lis2dux12 -> iodev ;
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- struct rtio_sqe * write_addr = rtio_sqe_acquire (rtio );
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- struct rtio_sqe * read_reg = rtio_sqe_acquire (rtio );
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- struct rtio_sqe * complete_op = rtio_sqe_acquire (rtio );
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- struct rtio_iodev_sqe * sqe = lis2dux12 -> streaming_sqe ;
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- uint8_t reg_bus = lis2dux12_bus_reg (lis2dux12 , reg );
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-
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- /* check we have been able to acquire sqe */
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- if (write_addr == NULL || read_reg == NULL || complete_op == NULL ) {
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- return ;
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- }
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-
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- rtio_sqe_prep_tiny_write (write_addr , iodev , RTIO_PRIO_NORM , & reg_bus , 1 , NULL );
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- write_addr -> flags = RTIO_SQE_TRANSACTION ;
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- rtio_sqe_prep_read (read_reg , iodev , RTIO_PRIO_NORM , buf , len , NULL );
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- read_reg -> flags = RTIO_SQE_CHAINED ;
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- if (lis2dux12 -> bus_type == BUS_I2C ) {
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- read_reg -> iodev_flags |= RTIO_IODEV_I2C_STOP | RTIO_IODEV_I2C_RESTART ;
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- }
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-
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- rtio_sqe_prep_callback_no_cqe (complete_op , complete_op_cb , (void * )dev , sqe );
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- rtio_submit (rtio , 0 );
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- }
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-
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void lis2dux12_submit_stream (const struct device * dev , struct rtio_iodev_sqe * iodev_sqe )
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{
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struct lis2dux12_data * lis2dux12 = dev -> data ;
@@ -180,19 +140,9 @@ static void lis2dux12_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe,
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}
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/* flush completion */
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- struct rtio_cqe * cqe ;
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int res = 0 ;
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- do {
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- cqe = rtio_cqe_consume (rtio );
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- if (cqe != NULL ) {
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- if ((cqe -> result < 0 ) && (res == 0 )) {
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- LOG_ERR ("Bus error: %d" , cqe -> result );
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- res = cqe -> result ;
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- }
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- rtio_cqe_release (rtio , cqe );
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- }
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- } while (cqe != NULL );
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+ res = rtio_flush_completion_queue (rtio );
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/* Bail/cancel attempt to read sensor on any error */
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if (res != 0 ) {
@@ -299,6 +249,19 @@ static void lis2dux12_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe,
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read_buf = buf + sizeof (hdr );
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buf_avail = buf_len - sizeof (hdr );
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+ uint8_t reg_addr = lis2dux12_bus_reg (lis2dux12 -> bus_type , LIS2DUXXX_DT_FIFO_DATA_OUT_TAG );
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+ struct rtio_regs fifo_regs ;
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+ struct rtio_regs_list regs_list [] = {
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+ {
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+ reg_addr ,
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+ read_buf ,
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+ buf_avail ,
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+ },
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+ };
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+
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+ fifo_regs .rtio_regs_list = regs_list ;
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+ fifo_regs .rtio_regs_num = ARRAY_SIZE (regs_list );
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+
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/*
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* Prepare rtio enabled bus to read all fifo_count entries from
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* LIS2DUX12_FIFO_DATA_OUT_TAG. Then lis2dux12_complete_op_cb
@@ -314,8 +277,8 @@ static void lis2dux12_read_fifo_cb(struct rtio *r, const struct rtio_sqe *sqe,
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* lis2dux12_fifo_out_raw_get(&dev_ctx, &f_data);
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* }
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*/
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- lis2dux12_rtio_rw_transaction ( dev , LIS2DUXXX_DT_FIFO_DATA_OUT_TAG ,
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- read_buf , buf_avail , lis2dux12_complete_op_cb );
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+ rtio_read_regs_async ( lis2dux12 -> rtio_ctx , lis2dux12 -> iodev , lis2dux12 -> bus_type ,
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+ & fifo_regs , lis2dux12 -> streaming_sqe , dev , lis2dux12_complete_op_cb );
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}
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/*
@@ -351,19 +314,9 @@ static void lis2dux12_read_status_cb(struct rtio *r, const struct rtio_sqe *sqe,
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}
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/* flush completion */
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- struct rtio_cqe * cqe ;
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int res = 0 ;
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- do {
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- cqe = rtio_cqe_consume (rtio );
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- if (cqe != NULL ) {
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- if ((cqe -> result < 0 ) && (res == 0 )) {
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- LOG_ERR ("Bus error: %d" , cqe -> result );
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- res = cqe -> result ;
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- }
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- rtio_cqe_release (rtio , cqe );
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- }
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- } while (cqe != NULL );
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+ res = rtio_flush_completion_queue (rtio );
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/* Bail/cancel attempt to read sensor on any error */
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if (res != 0 ) {
@@ -439,6 +392,19 @@ static void lis2dux12_read_status_cb(struct rtio *r, const struct rtio_sqe *sqe,
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memcpy (buf , & hdr , sizeof (hdr ));
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read_buf = (uint8_t * )& ((struct lis2dux12_rtio_data * )buf )-> acc [0 ];
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+ uint8_t reg_addr = lis2dux12_bus_reg (lis2dux12 -> bus_type , LIS2DUXXX_DT_OUTX_L );
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+ struct rtio_regs fifo_regs ;
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+ struct rtio_regs_list regs_list [] = {
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+ {
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+ reg_addr ,
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+ read_buf ,
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+ 6 ,
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+ },
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+ };
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+
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+ fifo_regs .rtio_regs_list = regs_list ;
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+ fifo_regs .rtio_regs_num = ARRAY_SIZE (regs_list );
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+
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/*
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* Prepare rtio enabled bus to read LIS2DUX12_OUTX_L_A register
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* where accelerometer data is available.
@@ -450,8 +416,9 @@ static void lis2dux12_read_status_cb(struct rtio *r, const struct rtio_sqe *sqe,
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*
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* lis2dux12_acceleration_raw_get(&dev_ctx, accel_raw);
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*/
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- lis2dux12_rtio_rw_transaction (dev , LIS2DUXXX_DT_OUTX_L ,
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- read_buf , 6 , lis2dux12_complete_op_cb );
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+ rtio_read_regs_async (lis2dux12 -> rtio_ctx , lis2dux12 -> iodev , lis2dux12 -> bus_type ,
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+ & fifo_regs , lis2dux12 -> streaming_sqe , dev ,
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+ lis2dux12_complete_op_cb );
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}
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}
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@@ -486,6 +453,20 @@ void lis2dux12_stream_irq_handler(const struct device *dev)
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if (lis2dux12 -> trig_cfg .int_fifo_th || lis2dux12 -> trig_cfg .int_fifo_full ) {
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lis2dux12 -> fifo_status [0 ] = lis2dux12 -> fifo_status [1 ] = 0 ;
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+ uint8_t reg_addr =
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+ lis2dux12_bus_reg (lis2dux12 -> bus_type , LIS2DUXXX_DT_FIFO_STATUS1 );
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+ struct rtio_regs fifo_regs ;
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+ struct rtio_regs_list regs_list [] = {
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+ {
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+ reg_addr ,
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+ lis2dux12 -> fifo_status ,
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+ 2 ,
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+ },
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+ };
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+
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+ fifo_regs .rtio_regs_list = regs_list ;
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+ fifo_regs .rtio_regs_num = ARRAY_SIZE (regs_list );
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+
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/*
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* Prepare rtio enabled bus to read LIS2DUX12_FIFO_STATUS1 and
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* LIS2DUX12_FIFO_STATUS2 registers where FIFO threshold condition and
@@ -500,14 +481,29 @@ void lis2dux12_stream_irq_handler(const struct device *dev)
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* uint16_t num;
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* lis2duxs12_fifo_data_level_get(&dev_ctx, &num);
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*/
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- lis2dux12_rtio_rw_transaction (dev , LIS2DUXXX_DT_FIFO_STATUS1 ,
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- lis2dux12 -> fifo_status , 2 , lis2dux12_read_fifo_cb );
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+ rtio_read_regs_async (lis2dux12 -> rtio_ctx , lis2dux12 -> iodev ,
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+ lis2dux12 -> bus_type , & fifo_regs ,
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+ lis2dux12 -> streaming_sqe , dev ,
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+ lis2dux12_read_fifo_cb );
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}
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/* handle drdy trigger */
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if (lis2dux12 -> trig_cfg .int_drdy ) {
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lis2dux12 -> status = 0 ;
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+ uint8_t reg_addr = lis2dux12_bus_reg (lis2dux12 -> bus_type , LIS2DUXXX_DT_STATUS );
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+ struct rtio_regs fifo_regs ;
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+ struct rtio_regs_list regs_list [] = {
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+ {
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+ reg_addr ,
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+ & lis2dux12 -> status ,
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+ 1 ,
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+ },
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+ };
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+
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+ fifo_regs .rtio_regs_list = regs_list ;
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+ fifo_regs .rtio_regs_num = ARRAY_SIZE (regs_list );
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+
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/*
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* Prepare rtio enabled bus to read LIS2DUX12_STATUS_REG register
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* where accelerometer and gyroscope data ready status is available.
@@ -519,7 +515,8 @@ void lis2dux12_stream_irq_handler(const struct device *dev)
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*
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* lis2dux12_flag_data_ready_get(&dev_ctx, &drdy);
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*/
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- lis2dux12_rtio_rw_transaction (dev , LIS2DUXXX_DT_STATUS ,
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- & lis2dux12 -> status , 1 , lis2dux12_read_status_cb );
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+ rtio_read_regs_async (lis2dux12 -> rtio_ctx , lis2dux12 -> iodev , lis2dux12 -> bus_type ,
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+ & fifo_regs , lis2dux12 -> streaming_sqe , dev ,
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+ lis2dux12_read_status_cb );
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}
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}
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