soc: arm64: add support of pinctrl for r8a779f

Add support of pinctrl for r8a779f.

Signed-off-by: Mykola Kvach <[email protected]>

Author: xakep-amatop

drivers/pinctrl/pfc_rcar.c

@@ -16,9 +16,20 @@
 DEVICE_MMIO_TOPLEVEL_STATIC(pfc, DT_DRV_INST(0));
 
 #define PFC_REG_BASE  DEVICE_MMIO_TOPLEVEL_GET(pfc)
+
+#ifdef CONFIG_SOC_R8A779F
+/*
+ * todo: add support of pin groups,the next registers
+ *       offset is for a group 0
+ */
+#define PFC_RCAR_PMMR 0x0
+#define PFC_RCAR_GPSR 0x040
+#define PFC_RCAR_IPSR 0x060
+#else
 #define PFC_RCAR_PMMR 0x0
 #define PFC_RCAR_GPSR 0x100
 #define PFC_RCAR_IPSR 0x200
+#endif
 
 /*
  * Each drive step is either encoded in 2 or 3 bits.

include/zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f.h

@@ -0,0 +1,32 @@
+/*
+ * Copyright (c) 2023 EPAM Systems
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#ifndef ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F_H_
+#define ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F_H_
+
+#include "pinctrl-rcar-common.h"
+
+/* Pins declaration */
+#define PIN_NONE           -1
+
+/*
+ * note: we don't need ipsr configuration for sd/mmc pins,
+ *       they don't have alternative functions.
+ */
+#define PIN_SD_WP          RCAR_GP_PIN(1, 24)
+#define PIN_SD_CD          RCAR_GP_PIN(1, 23)
+#define PIN_MMC_SD_CMD     RCAR_GP_PIN(1, 22)
+#define PIN_MMC_DS         RCAR_GP_PIN(1, 20)
+#define PIN_MMC_D7         RCAR_GP_PIN(1, 21)
+#define PIN_MMC_D6         RCAR_GP_PIN(1, 19)
+#define PIN_MMC_D5         RCAR_GP_PIN(1, 17)
+#define PIN_MMC_D4         RCAR_GP_PIN(1, 18)
+#define PIN_MMC_SD_D3      RCAR_GP_PIN(1, 16)
+#define PIN_MMC_SD_D2      RCAR_GP_PIN(1, 15)
+#define PIN_MMC_SD_D1      RCAR_GP_PIN(1, 14)
+#define PIN_MMC_SD_D0      RCAR_GP_PIN(1, 13)
+#define PIN_MMC_SD_CLK     RCAR_GP_PIN(1, 12)
+
+#endif /* ZEPHYR_INCLUDE_DT_BINDINGS_PINCTRL_RENESAS_PINCTRL_R8A779F_H_ */

soc/arm64/renesas_rcar/gen4/CMakeLists.txt

@@ -1,4 +1,5 @@
 # Copyright (c) 2023 EPAM Systems
 # SPDX-License-Identifier: Apache-2.0
 
+zephyr_library_sources_ifdef(CONFIG_SOC_R8A779F  pfc_r8a779f.c)
 zephyr_library_sources_ifdef(CONFIG_ARM_MMU      mmu_regions.c)

soc/arm64/renesas_rcar/gen4/Kconfig.defconfig.series

@@ -12,4 +12,7 @@ config NUM_IRQS
 	int
 	default 500
 
+config PINCTRL
+	default y
+
 endif # SOC_SERIES_RCAR_GEN4

soc/arm64/renesas_rcar/gen4/pfc_r8a779f.c

@@ -0,0 +1,71 @@
+/*
+ * Copyright (c) 2023 EPAM Systems
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#include "pinctrl_soc.h"
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-r8a779f.h>
+
+const struct pfc_drive_reg pfc_drive_regs[] = {
+	/* DRV1CTRL1 */
+	{ 0x884, {
+		  { PIN_MMC_SD_D2,  28, 3 },
+		  { PIN_MMC_SD_D1,  24, 3 },
+		  { PIN_MMC_SD_D0,  20, 3 },
+		  { PIN_MMC_SD_CLK, 16, 3 },
+	  } },
+	/* DRV2CTRL1 */
+	{ 0x888, {
+		  { PIN_SD_CD,      28, 3 },
+		  { PIN_MMC_SD_CMD, 24, 3 },
+		  { PIN_MMC_D7,     20, 3 },
+		  { PIN_MMC_DS,     16, 3 },
+		  { PIN_MMC_D6,     12, 3 },
+		  { PIN_MMC_D4,      8, 3 },
+		  { PIN_MMC_D5,      4, 3 },
+		  { PIN_MMC_SD_D3,   0, 3 },
+	  } },
+	/* DRV3CTRL1 */
+	{ 0x88c, {
+		  { PIN_SD_WP, 0, 3 },
+	  } },
+	{ },
+};
+
+#define PFC_BIAS_REG(r1, r2) \
+	.puen = r1,	     \
+	.pud = r2,	     \
+	.pins =
+
+const struct pfc_bias_reg pfc_bias_regs[] = {
+	/* PUEN1, PUD1 */
+	{ PFC_BIAS_REG(0x8c0, 0x8e0) {
+		  [0 ... 11] = PIN_NONE,
+		  [12] = PIN_MMC_SD_CLK,
+		  [13] = PIN_MMC_SD_D0,
+		  [14] = PIN_MMC_SD_D1,
+		  [15] = PIN_MMC_SD_D2,
+		  [16] = PIN_MMC_SD_D3,
+		  [17] = PIN_MMC_D5,
+		  [18] = PIN_MMC_D4,
+		  [19] = PIN_MMC_D6,
+		  [20] = PIN_MMC_DS,
+		  [21] = PIN_MMC_D7,
+		  [22] = PIN_MMC_SD_CMD,
+		  [23] = PIN_SD_CD,
+		  [24] = PIN_SD_WP,
+		  [25 ... 31] = PIN_NONE,
+	  } },
+	{ /* sentinel */ },
+};
+
+const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void)
+{
+	return pfc_bias_regs;
+}
+const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void)
+{
+	return pfc_drive_regs;
+}

soc/arm64/renesas_rcar/gen4/pinctrl_soc.h

@@ -0,0 +1,117 @@
+/*
+ * Copyright (c) 2023 EPAM Systems
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ */
+
+#ifndef ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
+#define ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_
+
+#include <zephyr/devicetree.h>
+#include <zephyr/dt-bindings/pinctrl/renesas/pinctrl-rcar-common.h>
+#include <stdint.h>
+#include <zephyr/sys/util_macro.h>
+
+struct rcar_pin_func {
+	uint8_t bank:5;      /* bank number 0 - 18 */
+	uint8_t shift:5;     /* bit shift 0 - 28 */
+	uint8_t func:4;      /* choice from 0x0 to 0xF */
+};
+/** Pull-up, pull-down, or bias disable is requested */
+#define RCAR_PIN_FLAGS_PULL_SET BIT(0)
+/** Performs on/off control of the pull resistors */
+#define RCAR_PIN_FLAGS_PUEN     BIT(1)
+/** Select pull-up resistor if set pull-down otherwise */
+#define RCAR_PIN_FLAGS_PUD      BIT(2)
+/** Alternate function for the pin is requested */
+#define RCAR_PIN_FLAGS_FUNC_SET BIT(3)
+
+#define RCAR_PIN_PULL_UP      (RCAR_PIN_FLAGS_PULL_SET | RCAR_PIN_FLAGS_PUEN | RCAR_PIN_FLAGS_PUD)
+#define RCAR_PIN_PULL_DOWN    (RCAR_PIN_FLAGS_PULL_SET | RCAR_PIN_FLAGS_PUEN)
+#define RCAR_PIN_PULL_DISABLE  RCAR_PIN_FLAGS_PULL_SET
+
+/** Type for R-Car pin. */
+typedef struct pinctrl_soc_pin {
+	uint16_t pin;
+	struct rcar_pin_func func;
+	uint8_t flags;
+	uint8_t drive_strength;
+} pinctrl_soc_pin_t;
+
+#define RCAR_IPSR(node_id) DT_PROP_BY_IDX(node_id, pin, 1)
+#define RCAR_HAS_IPSR(node_id) DT_PROP_HAS_IDX(node_id, pin, 1)
+
+/* Offsets are defined in dt-bindings pinctrl-rcar-common.h */
+#define RCAR_PIN_FUNC(node_id)			       \
+	{					       \
+		((RCAR_IPSR(node_id) >> 10U) & 0x1FU), \
+		((RCAR_IPSR(node_id) >> 4U) & 0x1FU),  \
+		((RCAR_IPSR(node_id) & 0xFU))	       \
+	}
+
+#define RCAR_PIN_FLAGS(node_id)						       \
+	DT_PROP(node_id, bias_pull_up)   * RCAR_PIN_PULL_UP |		       \
+	DT_PROP(node_id, bias_pull_down) * RCAR_PIN_PULL_DOWN |		       \
+	DT_PROP(node_id, bias_disable)   * RCAR_PIN_PULL_DISABLE |	       \
+	RCAR_HAS_IPSR(node_id) * RCAR_PIN_FLAGS_FUNC_SET
+
+#define RCAR_DT_PIN(node_id)						       \
+	{								       \
+		.pin = DT_PROP_BY_IDX(node_id, pin, 0),			       \
+		.func = COND_CODE_1(RCAR_HAS_IPSR(node_id),		       \
+				    (RCAR_PIN_FUNC(node_id)), ({0})),	       \
+		.flags = RCAR_PIN_FLAGS(node_id),			       \
+		.drive_strength =					       \
+			COND_CODE_1(DT_NODE_HAS_PROP(node_id, drive_strength), \
+				    (DT_PROP(node_id, drive_strength)), (0)),  \
+	},
+
+/**
+ * @brief Utility macro to initialize each pin.
+ *
+ * @param node_id Node identifier.
+ * @param state_prop State property name.
+ * @param idx State property entry index.
+ */
+#define Z_PINCTRL_STATE_PIN_INIT(node_id, state_prop, idx) \
+	RCAR_DT_PIN(DT_PROP_BY_IDX(node_id, state_prop, idx))
+
+/**
+ * @brief Utility macro to initialize state pins contained in a given property.
+ *
+ * @param node_id Node identifier.
+ * @param prop Property name describing state pins.
+ */
+#define Z_PINCTRL_STATE_PINS_INIT(node_id, prop) \
+	{ DT_FOREACH_PROP_ELEM(node_id, prop, Z_PINCTRL_STATE_PIN_INIT) }
+
+struct pfc_drive_reg_field {
+	uint16_t pin;
+	uint8_t offset;
+	uint8_t size;
+};
+
+struct pfc_drive_reg {
+	uint32_t reg;
+	const struct pfc_drive_reg_field fields[8];
+};
+
+struct pfc_bias_reg {
+	uint32_t puen;		/** Pull-enable or pull-up control register */
+	uint32_t pud;		/** Pull-up/down or pull-down control register */
+	const uint16_t pins[32];
+};
+
+const struct pfc_bias_reg *pfc_rcar_get_bias_regs(void);
+const struct pfc_drive_reg *pfc_rcar_get_drive_regs(void);
+
+/**
+ * @brief Utility macro to check if a pin is GPIO capable
+ *
+ * @param pin
+ * @return true if pin is GPIO capable false otherwise
+ */
+#define RCAR_IS_GP_PIN(pin) (pin < PIN_NOGPSR_START)
+
+#endif /* ZEPHYR_SOC_ARM_RENESAS_RCAR_GEN4_PINCTRL_SOC_H_ */