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Tavish Narukantavish
Tavish Naruka
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ntavish
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drivers: timer: add TMS570 RTI timer as system timer
Adds the RTI timer for TI TMS570 SoC and enables it as the system timer for enabling multithreading. Signed-off-by: Tavish Naruka <[email protected]>
1 parent 18cad3c commit eb39308

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7 files changed

+160
-3
lines changed

7 files changed

+160
-3
lines changed

‎drivers/timer/CMakeLists.txt‎

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@@ -41,6 +41,7 @@ zephyr_library_sources_ifdef(CONFIG_SAM0_RTC_TIMER sam0_rtc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_SILABS_SLEEPTIMER_TIMER silabs_sleeptimer_timer.c)
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zephyr_library_sources_ifdef(CONFIG_STM32_LPTIM_TIMER stm32_lptim_timer.c)
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zephyr_library_sources_ifdef(CONFIG_TI_DM_TIMER ti_dmtimer.c)
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zephyr_library_sources_ifdef(CONFIG_TMS570_RTI_TIMER tms570_rti_timer.c)
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zephyr_library_sources_ifdef(CONFIG_XLNX_PSTTC_TIMER xlnx_psttc_timer.c)
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zephyr_library_sources_ifdef(CONFIG_XTENSA_TIMER xtensa_sys_timer.c)
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zephyr_library_sources_ifdef(CONFIG_SMARTBOND_TIMER smartbond_timer.c)

‎drivers/timer/Kconfig‎

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@@ -99,6 +99,7 @@ source "drivers/timer/Kconfig.silabs"
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source "drivers/timer/Kconfig.smartbond"
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source "drivers/timer/Kconfig.stm32_lptim"
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source "drivers/timer/Kconfig.ti_dm_timer"
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source "drivers/timer/Kconfig.tms570_rti_timer"
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source "drivers/timer/Kconfig.xlnx_psttc"
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source "drivers/timer/Kconfig.xtensa"
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source "drivers/timer/Kconfig.mtk_adsp"

‎drivers/timer/Kconfig.tms570_rti_timer‎

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# Copyright (C) 2025 ispace, inc.
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#
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# SPDX-License-Identifier: Apache-2.0
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config TMS570_RTI_TIMER
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bool "TI TMS570 RTI Timer"
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default y
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depends on SOC_TI_TMS570LC43X
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help
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This module implements a kernel device driver for the TI TMS570 RTI
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timer.

‎drivers/timer/tms570_rti_timer.c‎

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/*
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* Copyright (c) 2025 ispace, inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <soc.h>
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#include <zephyr/init.h>
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#include <zephyr/spinlock.h>
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#include <zephyr/drivers/timer/system_timer.h>
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#include <zephyr/irq.h>
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#define DT_DRV_COMPAT ti_tms570_rti
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#define REG_RTI DT_INST_REG_ADDR_BY_IDX(0, 0)
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#define RTI_CLK_FREQ DT_PROP(DT_NODELABEL(clk_rticlk), clock_frequency)
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#define RTI_INTFLAG_COMP0 BIT(0)
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#define RTI_INTENA_COMP0 BIT(0)
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#define RTI_INTCLR_ALL (BIT(18) | BIT(17) | BIT(16) | \
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BIT(3) | BIT(2) | BIT(1) | BIT(0))
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#define RTIGCTRL (REG_RTI + 0x00)
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#define RTITBCTRL (REG_RTI + 0x04)
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#define RTICAPCTRL (REG_RTI + 0x08)
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#define RTICOMPCTRL (REG_RTI + 0x0C)
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#define RTISETINTENA (REG_RTI + 0x80)
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#define RTICLEARINTENA (REG_RTI + 0x84)
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#define RTIINTFLAG (REG_RTI + 0x88)
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#define RTIFRC0 (REG_RTI + 0x10)
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#define RTIUC0 (REG_RTI + 0x14)
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#define RTICPUC0 (REG_RTI + 0x18)
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#define RTICAFRC0 (REG_RTI + 0x20)
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#define RTICAUC0 (REG_RTI + 0x24)
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#define RTICOMP0 (REG_RTI + 0x50)
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#define RTIUDCP0 (REG_RTI + 0x54)
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#define RTIGCTRL_COS_OFFSET (15)
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#define CNT1EN BIT(1)
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#define CNT0EN BIT(0)
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static struct k_spinlock ticks_lock;
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static volatile uint64_t ticks;
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uint32_t sys_clock_elapsed(void)
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{
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return 0;
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}
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uint32_t sys_clock_cycle_get_32(void)
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{
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return sys_read32(RTIFRC0);
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}
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static void rti_compare0_isr(const void *arg)
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{
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ARG_UNUSED(arg);
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K_SPINLOCK(&ticks_lock) {
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ticks += k_ticks_to_cyc_floor32(1);
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}
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sys_write32(RTI_INTFLAG_COMP0, RTIINTFLAG);
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sys_clock_announce(1);
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}
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static int rti_timer_init(void)
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{
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/**
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* TODO Counter block 0 can be synchronized with Network Time (NTU),
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* we can make use of that.
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*/
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/* disable counters and interrupts */
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sys_write32(1 << RTIGCTRL_COS_OFFSET, RTIGCTRL);
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sys_write32(RTI_INTCLR_ALL, RTICLEARINTENA);
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/**
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* We use counter 0 and compare register 0.
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*/
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/* default compare control and capture control */
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sys_write32(0, RTICOMPCTRL);
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sys_write32(0, RTICAPCTRL);
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/* Initialize counter 0 */
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sys_write32(0, RTIUC0);
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sys_write32(0, RTIFRC0);
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sys_write32(0, RTITBCTRL);
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/**
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* Set up free running counter interrupt cycle.
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* UCx - up-counter or prescale counter - driven by RTICLK
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* CPUCx - compare up-counter, it acts like a prescaler over UCx
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* FRCx - when CPUCx value matches UCx, this reg is incremented by one
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* COMPx - this is compared with FRCx, a match generates an interrupt
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* UDCPx - UDCPx is added to COMPx when a match occues (COMPx matches FRCx),
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* so that we can generate periodic interrupts1
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*/
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sys_write32(RTI_CLK_FREQ / CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC - 1U, RTICPUC0);
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/* free running counter, compare match period = 10 ms */
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sys_write32(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC, RTICOMP0);
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sys_write32(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC / CONFIG_SYS_CLOCK_TICKS_PER_SEC, RTIUDCP0);
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/* Clear all pending interrupts */
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sys_write32(RTI_INTCLR_ALL, RTIINTFLAG);
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/* connect irq */
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IRQ_CONNECT(IRQ_RTI_COMPARE_0, IRQ_RTI_COMPARE_0, rti_compare0_isr, NULL, 0);
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irq_enable(IRQ_RTI_COMPARE_0);
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/* Enable interrupt */
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sys_write32(RTI_INTENA_COMP0, RTISETINTENA);
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/* Enable timer */
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sys_write32(sys_read32(RTIGCTRL) | CNT1EN | CNT0EN, RTIGCTRL);
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return 0;
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}
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SYS_INIT(rti_timer_init, PRE_KERNEL_2, CONFIG_SYSTEM_CLOCK_INIT_PRIORITY);

‎dts/arm/ti/tms570.dtsi‎

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<0xFFA04000 0x10>; /* POM_CONTROL_BASE */
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};
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rti: rti@fffffc00 {
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compatible = "ti,tms570-rti";
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reg = <0xfffffc00 256>;
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clock-frequency = <DT_FREQ_M(1)>;
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tick-frequency = <100>;
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status = "okay";
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};
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sram0: memory@8000000 {
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compatible = "mmio-sram";
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reg = <0x08000000 DT_SIZE_K(512)>;

‎dts/bindings/timer/ti,tms570-rti.yaml‎

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# Copyright (c) 2025 ispace, inc.
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# SPDX-License-Identifier: Apache-2.0
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description: Real-time interrupt for TMS570
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compatible: "ti,tms570-rti"
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include: [base.yaml]
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properties:
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clock-frequency:
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type: int
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description: Clock frequency of RTI up counter
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tick-frequency:
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type: int
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description: Frequency of RTI interrupt for system tick

‎soc/ti/hercules/ti_tms570lc43x/Kconfig.defconfig‎

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@@ -24,12 +24,11 @@ config USE_SWITCH
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config RUNTIME_NMI
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default y
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# 10ms OS tick from a 1MHz free-running clock
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config SYS_CLOCK_TICKS_PER_SEC
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default 100
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default $(dt_node_int_prop_int,/soc/rti@fffffc00,tick-frequency)
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/soc/rti,clock-frequency)
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default $(dt_node_int_prop_int,/soc/rti@fffffc00,clock-frequency)
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config NUM_IRQS
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# must be >= the highest interrupt number used

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