soc: ite: it8xxx2: enable firmware control mode for elpm

This commit enables firmware control mode for elpm by default.

Signed-off-by: Ren Chen <[email protected]>

Author: Chenhongren

soc/ite/ec/it8xxx2/soc.c

@@ -53,7 +53,11 @@ COND_CODE_1(DT_NODE_EXISTS(DT_INST(1, ite_it8xxx2_usbpd)), (2), (1))
 #define CLK_DIV_LOW_FIELDS(n)  FIELD_PREP(GENMASK(3, 0), n)
 
 #ifdef CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
-#define ELPM_BASE_ADDR          0xF03E00
+#define ELPM_BASE_ADDR         DT_REG_ADDR(DT_INST(0, ite_it8xxx2_power_elpm))
+#define ELPMF1_WAKE_UP_CTRL_3  0xF1
+#define FIRMWARE_CTRL_EN       BIT(1)
+#define FIRMWARE_CTRL_OUTPUT_H BIT(0)
+
 #define ELPMF5_INPUT_EN         0xF5
 #define XLPIN_INPUT_ENABLE_MASK GENMASK(5, 0)
 #endif /* CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED */
@@ -534,6 +538,16 @@ static int ite_it8xxx2_init(void)
 #endif /* (SOC_USBPD_ITE_PHY_PORT_COUNT > 0) */
 
 #ifdef CONFIG_SOC_IT8XXX2_GPIO_Q_GROUP_SUPPORTED
+#if DT_HAS_COMPAT_STATUS_OKAY(ite_it8xxx2_power_elpm)
+	/* drive xlpout high and then enable elpm firmware control mode if
+	 * the elpm node is marked as okay.
+	 */
+	sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3) | FIRMWARE_CTRL_OUTPUT_H,
+		   ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3);
+	sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3) | FIRMWARE_CTRL_EN,
+		   ELPM_BASE_ADDR + ELPMF1_WAKE_UP_CTRL_3);
+#endif /* DT_HAS_COMPAT_STATUS_OKAY(ite_it8xxx2_power_elpm) */
+
 	/* set gpio-q group as gpio by default */
 	sys_write8(sys_read8(ELPM_BASE_ADDR + ELPMF5_INPUT_EN) & ~XLPIN_INPUT_ENABLE_MASK,
 		   ELPM_BASE_ADDR + ELPMF5_INPUT_EN);