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5 | 5 | */
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6 | 6 |
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7 | 7 | #include <arm/armv8-m.dtsi>
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| 8 | +#include <zephyr/dt-bindings/adc/adc.h> |
| 9 | +#include <zephyr/dt-bindings/adc/stm32u5_adc.h> |
8 | 10 | #include <zephyr/dt-bindings/clock/stm32u3_clock.h>
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9 | 11 | #include <zephyr/dt-bindings/gpio/gpio.h>
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10 | 12 | #include <zephyr/dt-bindings/reset/stm32u3_reset.h>
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232 | 234 | status = "disabled";
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233 | 235 | };
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234 | 236 |
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| 237 | + adc1: adc@42028000 { |
| 238 | + compatible = "st,stm32n6-adc", "st,stm32-adc"; |
| 239 | + reg = <0x42028000 0x400>; |
| 240 | + clocks = <&rcc STM32_CLOCK(AHB2, 10)>; |
| 241 | + interrupts = <37 0>; |
| 242 | + #io-channel-cells = <1>; |
| 243 | + resolutions = <STM32_ADC_RES(12, 0x00) |
| 244 | + STM32_ADC_RES(10, 0x01) |
| 245 | + STM32_ADC_RES(8, 0x02) |
| 246 | + STM32_ADC_RES(6, 0x03)>; |
| 247 | + sampling-times = <2 3 7 12 24 47 247 1500>; |
| 248 | + st,adc-sequencer = "FULLY_CONFIGURABLE"; |
| 249 | + st,adc-oversampler = "OVERSAMPLER_EXTENDED"; |
| 250 | + status = "disabled"; |
| 251 | + }; |
| 252 | + |
| 253 | + adc2: adc@42028100 { |
| 254 | + compatible = "st,stm32n6-adc", "st,stm32-adc"; |
| 255 | + reg = <0x42028100 0x400>; |
| 256 | + clocks = <&rcc STM32_CLOCK(AHB2, 10)>; |
| 257 | + interrupts = <113 0>; |
| 258 | + #io-channel-cells = <1>; |
| 259 | + resolutions = <STM32_ADC_RES(12, 0x00) |
| 260 | + STM32_ADC_RES(10, 0x01) |
| 261 | + STM32_ADC_RES(8, 0x02) |
| 262 | + STM32_ADC_RES(6, 0x03)>; |
| 263 | + sampling-times = <2 3 7 12 24 47 247 1500>; |
| 264 | + st,adc-sequencer = "FULLY_CONFIGURABLE"; |
| 265 | + st,adc-oversampler = "OVERSAMPLER_EXTENDED"; |
| 266 | + status = "disabled"; |
| 267 | + }; |
| 268 | + |
235 | 269 | dac1: dac@42028400 {
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236 | 270 | compatible = "st,stm32-dac";
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237 | 271 | reg = <0x42028400 0x400>;
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