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tunguyen4585henrikbrixandersen
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dts: arm: nxp: add Flexcan support for S32Z27x
Add FlexCan nodes to S32Z27x devices Signed-off-by: Tu Nguyen Van <[email protected]>
1 parent ac056bb commit ee6620e

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4 files changed

+366
-2
lines changed

4 files changed

+366
-2
lines changed

‎drivers/can/Kconfig.mcux‎

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -31,10 +31,11 @@ config CAN_MCUX_FLEXCAN_WAIT_TIMEOUT
3131
config CAN_MAX_MB
3232
int "Maximum number of message buffers for concurrent active instances"
3333
default 16
34-
depends on SOC_SERIES_S32K3 || SOC_SERIES_S32K1
34+
depends on SOC_SERIES_S32K3 || SOC_SERIES_S32K1 || SOC_SERIES_S32ZE
3535
range 1 96 if SOC_SERIES_S32K3
3636
range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W
3737
range 1 64 if SOC_S32K142W || SOC_S32K144W
38+
range 1 128 if SOC_SERIES_S32ZE
3839
help
3940
Defines maximum number of message buffers for concurrent active instances.
4041

@@ -47,6 +48,7 @@ config CAN_MAX_FILTER
4748
range 1 96 if SOC_SERIES_S32K3
4849
range 1 32 if SOC_SERIES_S32K1 && !SOC_S32K142W && !SOC_S32K144W
4950
range 1 64 if SOC_S32K142W || SOC_S32K144W
51+
range 1 128 if SOC_SERIES_S32ZE
5052
help
5153
Defines maximum number of concurrent active RX filters
5254

‎dts/arm/nxp/nxp_s32z27x_r52.dtsi‎

Lines changed: 361 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -713,5 +713,366 @@
713713
interrupt-names = "rx_tx_mru", "error";
714714
clocks = <&clock NXP_S32_P5_CANXL_PE_CLK>;
715715
};
716+
717+
flexcan0: can@449a0000 {
718+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
719+
reg = <0x449a0000 0x4000>;
720+
clk-source = <0>;
721+
interrupts = <GIC_SPI 581 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
722+
<GIC_SPI 583 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
723+
<GIC_SPI 584 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
724+
<GIC_SPI 585 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
725+
<GIC_SPI 586 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
726+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
727+
"ored_64_95_mb", "ored_96_127_mb";
728+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
729+
status = "disabled";
730+
};
731+
732+
flexcan1: can@449b0000 {
733+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
734+
reg = <0x449b0000 0x4000>;
735+
clk-source = <0>;
736+
interrupts = <GIC_SPI 587 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
737+
<GIC_SPI 589 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
738+
<GIC_SPI 590 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
739+
<GIC_SPI 591 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
740+
<GIC_SPI 592 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
741+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
742+
"ored_64_95_mb", "ored_96_127_mb";
743+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
744+
status = "disabled";
745+
};
746+
747+
flexcan2: can@449c0000 {
748+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
749+
clk-source = <0>;
750+
reg = <0x449c0000 0x4000>;
751+
interrupts = <GIC_SPI 593 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
752+
<GIC_SPI 595 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
753+
<GIC_SPI 596 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
754+
<GIC_SPI 597 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
755+
<GIC_SPI 598 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
756+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
757+
"ored_64_95_mb", "ored_96_127_mb";
758+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
759+
status = "disabled";
760+
};
761+
762+
flexcan3: can@449d0000 {
763+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
764+
clk-source = <0>;
765+
reg = <0x449d0000 0x4000>;
766+
interrupts = <GIC_SPI 599 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
767+
<GIC_SPI 601 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
768+
<GIC_SPI 602 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
769+
<GIC_SPI 603 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
770+
<GIC_SPI 604 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
771+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
772+
"ored_64_95_mb", "ored_96_127_mb";
773+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
774+
status = "disabled";
775+
};
776+
777+
flexcan4: can@449e0000 {
778+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
779+
clk-source = <0>;
780+
reg = <0x449e0000 0x4000>;
781+
interrupts = <GIC_SPI 605 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
782+
<GIC_SPI 607 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
783+
<GIC_SPI 608 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
784+
<GIC_SPI 609 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
785+
<GIC_SPI 610 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
786+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
787+
"ored_64_95_mb", "ored_96_127_mb";
788+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
789+
status = "disabled";
790+
};
791+
792+
flexcan5: can@449f0000 {
793+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
794+
clk-source = <0>;
795+
reg = <0x449f0000 0x4000>;
796+
interrupts = <GIC_SPI 611 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
797+
<GIC_SPI 613 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
798+
<GIC_SPI 614 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
799+
<GIC_SPI 615 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
800+
<GIC_SPI 616 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
801+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
802+
"ored_64_95_mb", "ored_96_127_mb";
803+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
804+
status = "disabled";
805+
};
806+
807+
flexcan6: can@44ba0000 {
808+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
809+
clk-source = <0>;
810+
reg = <0x44ba0000 0x4000>;
811+
interrupts = <GIC_SPI 617 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
812+
<GIC_SPI 619 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
813+
<GIC_SPI 620 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
814+
<GIC_SPI 621 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
815+
<GIC_SPI 622 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
816+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
817+
"ored_64_95_mb", "ored_96_127_mb";
818+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
819+
status = "disabled";
820+
};
821+
822+
flexcan7: can@44bb0000 {
823+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
824+
clk-source = <0>;
825+
reg = <0x44bb0000 0x4000>;
826+
interrupts = <GIC_SPI 623 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
827+
<GIC_SPI 625 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
828+
<GIC_SPI 626 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
829+
<GIC_SPI 627 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
830+
<GIC_SPI 628 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
831+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
832+
"ored_64_95_mb", "ored_96_127_mb";
833+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
834+
status = "disabled";
835+
};
836+
837+
flexcan8: can@44bc0000 {
838+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
839+
clk-source = <0>;
840+
reg = <0x44bc0000 0x4000>;
841+
interrupts = <GIC_SPI 629 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
842+
<GIC_SPI 631 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
843+
<GIC_SPI 632 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
844+
<GIC_SPI 633 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
845+
<GIC_SPI 634 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
846+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
847+
"ored_64_95_mb", "ored_96_127_mb";
848+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
849+
status = "disabled";
850+
};
851+
852+
flexcan9: can@44bd0000 {
853+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
854+
clk-source = <0>;
855+
reg = <0x44bd0000 0x4000>;
856+
interrupts = <GIC_SPI 635 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
857+
<GIC_SPI 637 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
858+
<GIC_SPI 638 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
859+
<GIC_SPI 639 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
860+
<GIC_SPI 640 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
861+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
862+
"ored_64_95_mb", "ored_96_127_mb";
863+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
864+
status = "disabled";
865+
};
866+
867+
flexcan10: can@44be0000 {
868+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
869+
clk-source = <0>;
870+
reg = <0x44be0000 0x4000>;
871+
interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
872+
<GIC_SPI 643 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
873+
<GIC_SPI 644 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
874+
<GIC_SPI 645 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
875+
<GIC_SPI 646 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
876+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
877+
"ored_64_95_mb", "ored_96_127_mb";
878+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
879+
status = "disabled";
880+
};
881+
882+
flexcan11: can@44bf0000 {
883+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
884+
clk-source = <0>;
885+
reg = <0x44bf0000 0x4000>;
886+
interrupts = <GIC_SPI 647 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
887+
<GIC_SPI 649 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
888+
<GIC_SPI 650 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
889+
<GIC_SPI 651 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
890+
<GIC_SPI 652 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
891+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
892+
"ored_64_95_mb", "ored_96_127_mb";
893+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
894+
status = "disabled";
895+
};
896+
897+
flexcan12: can@44da0000 {
898+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
899+
clk-source = <0>;
900+
reg = <0x44da0000 0x4000>;
901+
interrupts = <GIC_SPI 653 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
902+
<GIC_SPI 655 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
903+
<GIC_SPI 656 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
904+
<GIC_SPI 657 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
905+
<GIC_SPI 658 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
906+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
907+
"ored_64_95_mb", "ored_96_127_mb";
908+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
909+
status = "disabled";
910+
};
911+
912+
flexcan13: can@44db0000 {
913+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
914+
clk-source = <0>;
915+
reg = <0x44db0000 0x4000>;
916+
interrupts = <GIC_SPI 659 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
917+
<GIC_SPI 661 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
918+
<GIC_SPI 662 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
919+
<GIC_SPI 663 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
920+
<GIC_SPI 664 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
921+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
922+
"ored_64_95_mb", "ored_96_127_mb";
923+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
924+
status = "disabled";
925+
};
926+
927+
flexcan14: can@44dc0000 {
928+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
929+
clk-source = <0>;
930+
reg = <0x44dc0000 0x4000>;
931+
interrupts = <GIC_SPI 665 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
932+
<GIC_SPI 667 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
933+
<GIC_SPI 668 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
934+
<GIC_SPI 669 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
935+
<GIC_SPI 670 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
936+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
937+
"ored_64_95_mb", "ored_96_127_mb";
938+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
939+
status = "disabled";
940+
};
941+
942+
flexcan15: can@44dd0000 {
943+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
944+
clk-source = <0>;
945+
reg = <0x44dd0000 0x4000>;
946+
interrupts = <GIC_SPI 671 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
947+
<GIC_SPI 673 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
948+
<GIC_SPI 674 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
949+
<GIC_SPI 675 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
950+
<GIC_SPI 676 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
951+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
952+
"ored_64_95_mb", "ored_96_127_mb";
953+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
954+
status = "disabled";
955+
};
956+
957+
flexcan16: can@44de0000 {
958+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
959+
clk-source = <0>;
960+
reg = <0x44de0000 0x4000>;
961+
interrupts = <GIC_SPI 677 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
962+
<GIC_SPI 679 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
963+
<GIC_SPI 680 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
964+
<GIC_SPI 681 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
965+
<GIC_SPI 682 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
966+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
967+
"ored_64_95_mb", "ored_96_127_mb";
968+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
969+
status = "disabled";
970+
};
971+
972+
flexcan17: can@44df0000 {
973+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
974+
clk-source = <0>;
975+
reg = <0x44df0000 0x4000>;
976+
interrupts = <GIC_SPI 683 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
977+
<GIC_SPI 685 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
978+
<GIC_SPI 686 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
979+
<GIC_SPI 687 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
980+
<GIC_SPI 688 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
981+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
982+
"ored_64_95_mb", "ored_96_127_mb";
983+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
984+
status = "disabled";
985+
};
986+
987+
flexcan18: can@44fa0000 {
988+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
989+
clk-source = <0>;
990+
reg = <0x44fa0000 0x4000>;
991+
interrupts = <GIC_SPI 689 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
992+
<GIC_SPI 691 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
993+
<GIC_SPI 692 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
994+
<GIC_SPI 693 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
995+
<GIC_SPI 694 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
996+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
997+
"ored_64_95_mb", "ored_96_127_mb";
998+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
999+
status = "disabled";
1000+
};
1001+
1002+
flexcan19: can@44fb0000 {
1003+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
1004+
clk-source = <0>;
1005+
reg = <0x44fb0000 0x4000>;
1006+
interrupts = <GIC_SPI 695 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1007+
<GIC_SPI 697 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1008+
<GIC_SPI 698 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1009+
<GIC_SPI 699 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1010+
<GIC_SPI 700 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1011+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
1012+
"ored_64_95_mb", "ored_96_127_mb";
1013+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
1014+
status = "disabled";
1015+
};
1016+
1017+
flexcan20: can@44fc0000 {
1018+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
1019+
clk-source = <0>;
1020+
reg = <0x44fc0000 0x4000>;
1021+
interrupts = <GIC_SPI 701 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1022+
<GIC_SPI 703 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1023+
<GIC_SPI 704 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1024+
<GIC_SPI 705 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1025+
<GIC_SPI 706 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1026+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
1027+
"ored_64_95_mb", "ored_96_127_mb";
1028+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
1029+
status = "disabled";
1030+
};
1031+
1032+
flexcan21: can@44fd0000 {
1033+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
1034+
clk-source = <0>;
1035+
reg = <0x44fd0000 0x4000>;
1036+
interrupts = <GIC_SPI 707 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1037+
<GIC_SPI 709 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1038+
<GIC_SPI 710 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1039+
<GIC_SPI 711 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1040+
<GIC_SPI 712 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1041+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
1042+
"ored_64_95_mb", "ored_96_127_mb";
1043+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
1044+
status = "disabled";
1045+
};
1046+
1047+
flexcan22: can@44fe0000 {
1048+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
1049+
clk-source = <0>;
1050+
reg = <0x44fe0000 0x4000>;
1051+
interrupts = <GIC_SPI 713 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1052+
<GIC_SPI 715 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1053+
<GIC_SPI 716 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1054+
<GIC_SPI 717 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1055+
<GIC_SPI 718 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1056+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
1057+
"ored_64_95_mb", "ored_96_127_mb";
1058+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
1059+
status = "disabled";
1060+
};
1061+
1062+
flexcan23: can@44ff0000 {
1063+
compatible = "nxp,flexcan-fd", "nxp,flexcan";
1064+
clk-source = <0>;
1065+
reg = <0x44ff0000 0x4000>;
1066+
interrupts = <GIC_SPI 719 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1067+
<GIC_SPI 721 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1068+
<GIC_SPI 722 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1069+
<GIC_SPI 723 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>,
1070+
<GIC_SPI 724 IRQ_TYPE_LEVEL IRQ_DEFAULT_PRIORITY>;
1071+
interrupt-names = "ored", "ored_0_31_mb", "ored_32_63_mb",
1072+
"ored_64_95_mb", "ored_96_127_mb";
1073+
clocks = <&clock NXP_S32_P3_CAN_PE_CLK>;
1074+
status = "disabled";
1075+
};
1076+
7161077
};
7171078
};

‎soc/nxp/s32/s32ze/Kconfig‎

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -16,6 +16,7 @@ config SOC_SERIES_S32ZE
1616
select HAS_NXP_S32_HAL
1717
select HAS_MCUX
1818
select HAS_MCUX_PIT
19+
select HAS_MCUX_FLEXCAN
1920

2021
if SOC_SERIES_S32ZE
2122

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