intc: add vim_tms570 interrupt controller driver

This driver is not compatible with the existing intc_vim.c.

Signed-off-by: Tavish Naruka <[email protected]>

Author: Tavish Naruka

drivers/interrupt_controller/CMakeLists.txt

@@ -42,6 +42,7 @@ zephyr_library_sources_ifdef(CONFIG_NXP_S32_WKPU            intc_wkpu_nxp_s32.c)
 zephyr_library_sources_ifdef(CONFIG_XMC4XXX_INTC            intc_xmc4xxx.c)
 zephyr_library_sources_ifdef(CONFIG_NXP_PINT                intc_nxp_pint.c)
 zephyr_library_sources_ifdef(CONFIG_RENESAS_RZ_EXT_IRQ      intc_renesas_rz_ext_irq.c)
+zephyr_library_sources_ifdef(CONFIG_TMS570_VIM              intc_tms570_vim.c)
 zephyr_library_sources_ifdef(CONFIG_NXP_IRQSTEER            intc_nxp_irqsteer.c)
 zephyr_library_sources_ifdef(CONFIG_INTC_MTK_ADSP           intc_mtk_adsp.c)
 zephyr_library_sources_ifdef(CONFIG_WCH_PFIC                intc_wch_pfic.c)

drivers/interrupt_controller/Kconfig

@@ -104,6 +104,8 @@ source "drivers/interrupt_controller/Kconfig.vim"
 
 source "drivers/interrupt_controller/Kconfig.renesas_rz"
 
+source "drivers/interrupt_controller/Kconfig.tms570_vim"
+
 source "drivers/interrupt_controller/Kconfig.nxp_irqsteer"
 
 source "drivers/interrupt_controller/Kconfig.mtk_adsp"

drivers/interrupt_controller/Kconfig.tms570_vim

@@ -0,0 +1,15 @@
+# Copyright (C) 2025 ispace, inc.
+#
+# SPDX-License-Identifier: Apache-2.0
+
+if CPU_CORTEX_R5
+
+config TMS570_VIM
+	bool "TI Vectored Interrupt Manager (TMS570)"
+	default y
+	depends on DT_HAS_TI_TMS570_VIM_ENABLED
+	help
+		The TI Vectored Interrupt Manager provides hardware assistance for prioritizing
+		and aggregating the interrupt sources for TI herules ARM Cortex-R4/R5 processor cores.
+
+endif # CPU_CORTEX_R5

drivers/interrupt_controller/intc_tms570_vim.c

@@ -0,0 +1,150 @@
+/*
+ * Copyright (C) 2025 ispace, inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+#include <zephyr/irq.h>
+#include <zephyr/devicetree.h>
+#include <string.h>
+
+#define DT_DRV_COMPAT ti_tms570_vim
+
+#define DRV_CONTROL_REG		DT_INST_REG_ADDR_BY_IDX(0, 0)
+#define DRV_ECC_REG		DT_INST_REG_ADDR_BY_IDX(0, 1)
+#define DRV_VIMRAM_REG		DT_INST_REG_ADDR_BY_IDX(0, 2)
+#define DRV_VIMRAM_REG_SIZE	DT_INST_REG_SIZE_BY_IDX(0, 2)
+
+/* control registers */
+#define VIM_REG_IRQINDEX	(DRV_CONTROL_REG + 0x00)
+#define VIM_REG_FIQINDEX	(DRV_CONTROL_REG + 0x04)
+#define VIM_REG_REQMASKSET_0	(DRV_CONTROL_REG + 0x30) /* 0,1,2,3 in sequence, each is a 4 byte register*/
+#define VIM_REG_REQMASKCLR_0	(DRV_CONTROL_REG + 0x40) /* 0,1,2,3 in sequence, each is a 4 byte register*/
+
+/* ECC related registers */
+#define VIM_ECC_CTL		(DRV_ECC_REG + 0xF0)
+
+#define REQUMASK_IRQ_PER_REG	(32u)
+
+static inline void set_reqmask_bit(unsigned int irq, uintptr_t reg_0_addr)
+{
+	sys_write32(1 << (irq % REQUMASK_IRQ_PER_REG),
+		  reg_0_addr + (irq / REQUMASK_IRQ_PER_REG) * sizeof(uint32_t));
+}
+
+static inline int get_reqmask_bit(unsigned int irq, uintptr_t reg_0_addr)
+{
+	return sys_read32(reg_0_addr + (irq / REQUMASK_IRQ_PER_REG) * sizeof(uint32_t));
+}
+
+/* count of number of times the phantom interrupt happened */
+unsigned int nr_phantom_isr;
+
+static void phantom_isr(void)
+{
+	/**
+	 * we don't want this to call the z_spurious_irq because we have seen
+	 * phantom irq happen even though we don't expect it to happen.
+	 */
+	nr_phantom_isr++;
+}
+
+#if defined(CONFIG_RUNTIME_NMI)
+static void tms570_nmi_handler(void)
+{
+	while (1) {
+		/* forever */
+	}
+}
+#endif
+
+/**
+ * @brief Get active interrupt ID (IRQ only)
+ *
+ * @return Returns the ID of an active interrupt
+ */
+unsigned int z_soc_irq_get_active(void)
+{
+	unsigned int irq_idx;
+
+	/* a 0 means phantom ISR, channel 0 starts from index 1 */
+	irq_idx = sys_read32(VIM_REG_IRQINDEX);
+	if (irq_idx > 0) {
+		z_soc_irq_disable(irq_idx - 1);
+		return irq_idx - 1;
+
+	} else {
+		phantom_isr();
+	}
+
+	return (CONFIG_NUM_IRQS + 1);
+}
+
+void z_soc_irq_priority_set(unsigned int irq, unsigned int prio, uint32_t flags)
+{
+	/**
+	 * not supported, all IRQ sources generate IRQ, instead of FIQ,
+	 * and with the default priority.
+	 */
+}
+
+void z_soc_irq_enable(unsigned int irq)
+{
+	set_reqmask_bit(irq, VIM_REG_REQMASKSET_0);
+}
+
+void z_soc_irq_disable(unsigned int irq)
+{
+	set_reqmask_bit(irq, VIM_REG_REQMASKCLR_0);
+}
+
+int z_soc_irq_is_enabled(unsigned int irq)
+{
+	return get_reqmask_bit(irq, VIM_REG_REQMASKSET_0);
+}
+
+/**
+ * @brief Signal end-of-interrupt
+ *
+ * @param irq interrupt ID
+ */
+void z_soc_irq_eoi(unsigned int irq)
+{
+	z_soc_irq_enable(irq);
+}
+
+void z_soc_irq_init(void)
+{
+	/**
+	 * ref. SPNA218.pdf
+	 * We are implementing what is referred to as "Legacy ARM7 Interrupts".
+	 * We do not use the VIM_RAM at all.
+	 * Sequence is like this:
+	 * 1. Interrupt request happens
+	 * 2. Exception vector 0x18 (IRQ) or 0x1C (FIQ) is taken
+	 *      - in case of IRQ "ldr pc, =_isr_wrapper"
+	 *      - in case of FIQ "ldr pc, =z_arm_nmi"
+	 * 3. _isr_wrapper uses z_soc_irq_get_active to get index into
+	 *    _sw_isr_table for arg and ISR handler
+	 * 4. run ISR handler
+	 *
+	 * Drivers attach interrupts using IRQ_CONNECT/IRQ_DIRECT_CONNECT like:
+	 * 	IRQ_CONNECT(irqnum, irqnum, z_irq_spurious, NULL, 0);
+	 */
+
+	/* Errata VIM#28 Workaround: Disable Single Bit error correction */
+	sys_write32((0xAU << 0U) | (0x5U << 16U), VIM_ECC_CTL);
+
+	/*
+	   spent a long time debugging a ESM2.25 NMI fault which is
+	   "CCM-R5F VIM compare error". Could not find cause but this
+	   seems to have made it stop.
+	*/
+	memset((void *)DRV_VIMRAM_REG, 0, DRV_VIMRAM_REG_SIZE);
+
+#if defined(CONFIG_RUNTIME_NMI)
+	z_arm_nmi_set_handler(tms570_nmi_handler);
+#endif
+
+	/* enable interrupt */
+	arch_irq_unlock(0);
+}

dts/arm/ti/tms570.dtsi

@@ -72,13 +72,24 @@
 			reg = <0xffff1c00 0x400>;
 			status = "okay";
 		};
+		
+		vim: interrupt-controller@fffffe00 {
+				compatible = "ti,tms570-vim";
+				reg = <0xfffffe00 0x00000100>, /* VIM control */
+				<0xfffffd00 0x00000100>, /* ECC related */
+				<0xfff82000 128>;      /* VIM_RAM     */
+				status = "okay";
+				interrupt-controller;
+				#interrupt-cells = <2>;
+				#address-cells = <1>;
+		};
 
 		sci1: uart@fff7e400 {
 			compatible = "ti,tms570-uart";
 			reg = <0xfff7e400 256>;
 			status = "disabled";
 		};
-		
+
 		sci3: uart@fff7e500 {
 			compatible = "ti,tms570-uart";
 			reg = <0xfff7e500 256>;

dts/bindings/interrupt-controller/ti,tms570-vim.yaml

@@ -0,0 +1,24 @@
+# Copyright (c) 2025 ispace, inc.
+# SPDX-License-Identifier: Apache-2.0
+
+description: VIM for TMS570
+
+compatible: "ti,tms570-vim"
+
+include: [interrupt-controller.yaml, base.yaml]
+
+
+properties:
+  # NOTE: Register ranges:
+  #        - 0 : VIM control registers
+  #        - 1 : VIM ECC related registers
+  #        - 2 : VIM RAM
+  reg:
+    required: true
+
+  "#interrupt-cells":
+    const: 2
+
+interrupt-cells:
+  - irq
+  - priority

soc/ti/hercules/tms570lc43x/Kconfig

@@ -13,7 +13,7 @@ config SOC_TI_TMS570LC43X
 	select PLATFORM_SPECIFIC_INIT
 	select PLATFORM_SPECIFIC_PRE_STACK_INIT
 	# select CPU_HAS_FPU
-	# select ARM_CUSTOM_INTERRUPT_CONTROLLER
+	select ARM_CUSTOM_INTERRUPT_CONTROLLER
 	imply XIP
 
 if SOC_TI_TMS570LC43X

soc/ti/hercules/tms570lc43x/Kconfig.defconfig

@@ -4,18 +4,33 @@
 if SOC_TI_TMS570LC43X
 
 config SYS_CLOCK_EXISTS
-	default n
+	default y
 
 config MULTITHREADING
+	default y
+
+config DYNAMIC_INTERRUPTS
 	default n
 
 config GEN_SW_ISR_TABLE
-	default n
+	default y
 
 config GEN_ISR_TABLES
+	default y
+
+config GEN_IRQ_VECTOR_TABLE
 	default n
 
-# launchpad is 16MHz
+config USE_SWITCH
+	default n
+
+config RUNTIME_NMI
+	default y
+
+# 10ms OS tick from a 1MHz free-running clock
+config SYS_CLOCK_TICKS_PER_SEC
+	default 100
+
 config SYS_CLOCK_HW_CYCLES_PER_SEC
 	default 16000000
 

soc/ti/hercules/tms570lc43x/soc.h

@@ -11,4 +11,16 @@
 #include <stdint.h>
 #define __GIC_PRESENT 0
 
+/* these are the default "Interrupt request assignments", see table in datasheet with same name */
+#define IRQ_NUM_ESM_HIGH	0 /* cannot be remapped, is NMI (FIQ) 		*/
+#define IRQ_RTI_COMPARE_0	2 /* RTI1 compare interrupt 0 			*/
+#define IRQ_RTI_COMPARE_1	3 /* RTI1 compare interrupt 1 			*/
+#define IRQ_RTI_COMPARE_2	4 /* RTI1 compare interrupt 2 			*/
+#define IRQ_RTI_COMPARE_3	5 /* RTI1 compare interrupt 3 			*/
+#define IRQ_RTI_OVERFLOW_0	6 /* RTI1 overflow interrupt 1			*/
+#define IRQ_RTI_OVERFLOW_1	7 /* RTI1 overflow interrupt 1			*/
+#define IRQ_RTI_TIME_BASE	8 /* RTI1 time-base				*/
+#define IRQ_GIO_HIGH_LEVEL	9 /* GIO high level interrupt			*/
+#define IRQ_NUM_ESM_LOW		20 /* ESM low level interrupt	 		*/
+
 #endif /* __TMS570_SOC_H__ */

subsys/testsuite/include/zephyr/interrupt_util.h

@@ -202,7 +202,9 @@ static inline void trigger_irq(int irq)
 	z_mips_enter_irq(irq);
 }
 
-#elif defined(CONFIG_CPU_CORTEX_R5) && defined(CONFIG_VIM)
+#elif defined(CONFIG_CPU_CORTEX_R5)
+
+#if defined(CONFIG_VIM)
 
 extern void z_vim_arm_enter_irq(int);
 
@@ -211,6 +213,17 @@ static inline void trigger_irq(int irq)
 	z_vim_arm_enter_irq(irq);
 }
 
+#elif defined(CONFIG_TMS570_VIM)
+
+extern void z_tms570_vim_arm_enter_irq(int);
+
+static inline void trigger_irq(int irq)
+{
+	z_tms570_vim_arm_enter_irq(irq);
+}
+
+#endif
+
 #else
 /* So far, Nios II does not support this */
 #define NO_TRIGGER_FROM_SW