@@ -176,8 +176,6 @@ struct uhc_dwc2_chan {
176176 uint8_t chan_cmd_processing : 1 ;
177177 /* XFER: pending, in-flight or done */
178178 uint8_t has_xfer : 1 ;
179- /* Pipe event is pending */
180- uint8_t event_pending : 1 ;
181179 /* Is channel enabled */
182180 uint8_t active : 1 ;
183181 /* Halt has been requested */
@@ -192,7 +190,7 @@ struct uhc_dwc2_data {
192190 /* Mutex for port access */
193191 struct k_mutex mutex ;
194192 /* Main events the driver thread waits for */
195- struct k_event drv_evt ;
193+ struct k_event event ;
196194 struct uhc_dwc2_chan chan [UHC_DWC2_MAX_CHAN ];
197195 /* Bit mask of channels with pending interrupts */
198196 uint32_t pending_channel_intrs_msk ;
@@ -210,8 +208,6 @@ struct uhc_dwc2_data {
210208 uint8_t num_chans_queued ;
211209 /* Debounce lock */
212210 uint8_t lock_enabled : 1 ;
213- /* Port event is pending */
214- uint8_t event_pending : 1 ;
215211 /* Device is connected */
216212 uint8_t conn_dev_ena : 1 ;
217213 /* Waiting to be disabled */
@@ -1088,8 +1084,7 @@ static void uhc_dwc2_handle_chan_intr(const struct device *dev, struct uhc_dwc2_
10881084 break ;
10891085 }
10901086 chan -> last_event = chan_event ;
1091- chan -> event_pending = 1 ;
1092- k_event_post (& priv -> drv_evt , BIT (UHC_DWC2_EVENT_CHAN0 ));
1087+ k_event_post (& priv -> event , BIT (UHC_DWC2_EVENT_CHAN0 ));
10931088 break ;
10941089 case DWC2_CHAN_EVENT_ERROR :
10951090 LOG_ERR ("Channel error handling not implemented yet" );
@@ -1189,8 +1184,7 @@ static void uhc_dwc2_isr_handler(const struct device *dev)
11891184 port_event = uhc_dwc2_decode_hprt (dev , core_event );
11901185 if (port_event != UHC_PORT_EVENT_NONE ) {
11911186 priv -> last_event = port_event ;
1192- priv -> event_pending = 1 ;
1193- k_event_post (& priv -> drv_evt , BIT (UHC_DWC2_EVENT_PORT ));
1187+ k_event_post (& priv -> event , BIT (UHC_DWC2_EVENT_PORT ));
11941188 }
11951189 } else {
11961190 /* No core event, nothing to do. Should never occur */
@@ -1232,31 +1226,25 @@ static inline enum uhc_port_event uhc_dwc2_get_port_event(const struct device *d
12321226 struct uhc_dwc2_data * priv = uhc_get_private (dev );
12331227 enum uhc_port_event port_event = UHC_PORT_EVENT_NONE ;
12341228
1235- /* TODO: enter critial section */
1236- if (priv -> event_pending ) {
1237- priv -> event_pending = 0 ;
1238- port_event = priv -> last_event ;
1229+ port_event = priv -> last_event ;
12391230
1240- switch (port_event ) {
1241- case UHC_PORT_EVENT_CONNECTION :
1242- /* Don't update state immediately, we still need to debounce. */
1243- if (uhc_dwc2_port_debounce (dev )) {
1244- port_event = UHC_PORT_EVENT_CONNECTION ;
1245- } else {
1246- LOG_ERR ("Port is not connected after debounce" );
1247- /* TODO: Simulate and/or verify */
1248- LOG_WRN ("Port debounce error handling is not implemented yet" );
1249- }
1250- break ;
1251- case UHC_PORT_EVENT_DISCONNECTION :
1252- case UHC_PORT_EVENT_ERROR :
1253- case UHC_PORT_EVENT_OVERCURRENT :
1254- break ;
1255- default :
1256- break ;
1231+ switch (port_event ) {
1232+ case UHC_PORT_EVENT_CONNECTION :
1233+ /* Don't update state immediately, we still need to debounce. */
1234+ if (uhc_dwc2_port_debounce (dev )) {
1235+ port_event = UHC_PORT_EVENT_CONNECTION ;
1236+ } else {
1237+ LOG_ERR ("Port is not connected after debounce" );
1238+ /* TODO: Simulate and/or verify */
1239+ LOG_WRN ("Port debounce error handling is not implemented yet" );
12571240 }
1258- } else {
1259- port_event = UHC_PORT_EVENT_NONE ;
1241+ break ;
1242+ case UHC_PORT_EVENT_DISCONNECTION :
1243+ case UHC_PORT_EVENT_ERROR :
1244+ case UHC_PORT_EVENT_OVERCURRENT :
1245+ break ;
1246+ default :
1247+ break ;
12601248 }
12611249
12621250 /* TODO: exit critical section */
@@ -1679,18 +1667,18 @@ static inline void uhc_dwc2_thread_handler(void *const arg)
16791667 struct uhc_dwc2_data * const priv = uhc_get_private (dev );
16801668 uint32_t evt ;
16811669
1682- evt = k_event_wait (& priv -> drv_evt , UINT32_MAX , false, K_FOREVER );
1670+ evt = k_event_wait (& priv -> event , UINT32_MAX , false, K_FOREVER );
16831671
16841672 uhc_lock_internal (dev , K_FOREVER );
16851673
16861674 if (evt & BIT (UHC_DWC2_EVENT_PORT )) {
1687- k_event_clear (& priv -> drv_evt , BIT (UHC_DWC2_EVENT_PORT ));
1675+ k_event_clear (& priv -> event , BIT (UHC_DWC2_EVENT_PORT ));
16881676 uhc_dwc2_handle_port_events (dev );
16891677 }
16901678
16911679 for (uint32_t i = 0 ; i < 32 ; i ++ ) {
16921680 if (evt & BIT (UHC_DWC2_EVENT_CHAN0 + i )) {
1693- k_event_clear (& priv -> drv_evt , BIT (UHC_DWC2_EVENT_CHAN0 + i ));
1681+ k_event_clear (& priv -> event , BIT (UHC_DWC2_EVENT_CHAN0 + i ));
16941682 uhc_dwc2_handle_chan_events (dev , & priv -> chan [i ]);
16951683 }
16961684 }
@@ -1831,7 +1819,7 @@ static int uhc_dwc2_preinit(const struct device *dev)
18311819 memset (priv , 0 , sizeof (struct uhc_dwc2_data ));
18321820 k_mutex_init (& data -> mutex );
18331821 k_mutex_init (& priv -> mutex );
1834- k_event_init (& priv -> drv_evt );
1822+ k_event_init (& priv -> event );
18351823
18361824 /* TODO: Overwrite the DWC2 register values with the devicetree values? */
18371825
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