boards: beaglev_fire: fix memory address

Per the docs, the memory at address 0x80000000 ends at 0xC0000000.
In other words, the address space is 0x40000000, which is only half
of the size we want to map. This means that the upper address space
previously mapped was overlapping with the space reserved for non-cached
memory.

Instead, we map the entire 2GB at 0x1000000000, which is the correct
address for cached DDR that occupies more than 1 GB.

We defined a new node in the device tree for this memory region,
`beaglev.ddr_cached_high`. We did not reuse the `soc` node because
we needed to redefine the `#address-cells` to be 2, and doing so
would have affected other nodes under `soc`.

Signed-off-by: Alex Charlton <[email protected]>

Author: AlexCharlton

boards/beagle/beaglev_fire/beaglev_fire_common.dtsi

@@ -15,17 +15,20 @@
 	aliases {
 	};
 
-	soc {
-		sram1: memory@80000000 {
+	beaglev {
+		#address-cells = <2>;
+		#size-cells = <1>;
+
+		ddr_cached_high: memory@1000000000 {
 			compatible = "mmio-sram";
-			reg = <0x80000000 0x77F80000>; /* Size = 2GB - 0x80000 */
+			reg = <0x10 0x00000000 0x80000000>; /* 2GB */
 		};
 	};
 
 	chosen {
 		zephyr,console = &uart0;
 		zephyr,shell-uart = &uart0;
-		zephyr,sram = &sram1;
+		zephyr,sram = &ddr_cached_high;
 	};
 };
 

boards/beagle/beaglev_fire/beaglev_fire_polarfire_e51.yaml

@@ -4,7 +4,7 @@ type: mcu
 arch: riscv
 toolchain:
   - zephyr
-ram: 2012741
+ram: 2048000
 testing:
   ignore_tags:
     - net

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54.yaml

@@ -4,7 +4,7 @@ type: mcu
 arch: riscv
 toolchain:
   - zephyr
-ram: 2012741
+ram: 2048000
 testing:
   ignore_tags:
     - net

boards/beagle/beaglev_fire/beaglev_fire_polarfire_u54_smp.yaml

@@ -4,7 +4,7 @@ type: mcu
 arch: riscv
 toolchain:
   - zephyr
-ram: 2012741
+ram: 2048000
 testing:
   ignore_tags:
     - net

boards/beagle/beaglev_fire/doc/index.rst

@@ -93,12 +93,12 @@ When using the PolarFire `Hart Software Services <https://github.com/polarfire-s
 
   # Define the entry point address for each hart (U54 cores)
   hart-entry-points:
-    u54_1: '0x80000000'
+    u54_1: '0x1000000000'
 
   # Define the payloads (ELF binaries or raw blobs)
   payloads:
     <path_to_zephyr.elf>:
-      exec-addr: '0x80000000'  # Where Zephyr should be loaded
+      exec-addr: '0x1000000000'  # Where Zephyr should be loaded
       owner-hart: u54_1  # Primary hart that runs Zephyr
       priv-mode: prv_m  # Start in Machine mode
       skip-opensbi: true  # Boot directly without OpenSBI