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marwaiehm-stdleach02
marwaiehm-st
authored and
dleach02
committed
drivers: ethernet: eth_stm32_hal: Use the compatible st_stm32h7_ethernet
Replace "CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X" by the compatble st_stm32h7_ethernet Signed-off-by: IBEN EL HADJ MESSAOUD Marwa <[email protected]>
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-44
lines changed

1 file changed

+44
-44
lines changed

‎drivers/ethernet/eth_stm32_hal.c‎

Lines changed: 44 additions & 44 deletions
Original file line numberDiff line numberDiff line change
@@ -65,7 +65,7 @@ static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
6565

6666
#endif
6767

68-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
68+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
6969

7070
#define PHY_BSR ((uint16_t)0x0001U) /*!< Transceiver Basic Status Register */
7171
#define PHY_LINKED_STATUS ((uint16_t)0x0004U) /*!< Valid link established */
@@ -80,7 +80,7 @@ static const struct device *eth_stm32_phy_dev = DEVICE_PHY_BY_NAME(0);
8080
#define IS_ETH_DMATXDESC_OWN(dma_tx_desc) (dma_tx_desc->Status & \
8181
ETH_DMATXDESC_OWN)
8282

83-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
83+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
8484

8585
#define ETH_DMA_TX_TIMEOUT_MS 20U /* transmit timeout in milliseconds */
8686

@@ -228,7 +228,7 @@ static inline void setup_mac_filter(ETH_HandleTypeDef *heth)
228228
{
229229
__ASSERT_NO_MSG(heth != NULL);
230230

231-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
231+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
232232
ETH_MACFilterConfigTypeDef MACFilterConf;
233233

234234
HAL_ETH_GetMACFilterConfig(heth, &MACFilterConf);
@@ -269,7 +269,7 @@ static inline void setup_mac_filter(ETH_HandleTypeDef *heth)
269269
tmp = heth->Instance->MACFFR;
270270
k_sleep(K_MSEC(1));
271271
heth->Instance->MACFFR = tmp;
272-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X) */
272+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
273273
}
274274

275275
#if defined(CONFIG_PTP_CLOCK_STM32_HAL)
@@ -779,9 +779,9 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
779779
__ASSERT_NO_MSG(heth != NULL);
780780

781781
uint32_t dma_error;
782-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
782+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
783783
uint32_t mac_error;
784-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
784+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
785785
const uint32_t error_code = HAL_ETH_GetError(heth);
786786

787787
struct eth_stm32_hal_dev_data *dev_data =
@@ -791,7 +791,7 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
791791
case HAL_ETH_ERROR_DMA:
792792
dma_error = HAL_ETH_GetDMAError(heth);
793793

794-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
794+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
795795
if ((dma_error & ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG) ||
796796
(dma_error & ETH_DMA_RX_PROCESS_STOPPED_FLAG) ||
797797
(dma_error & ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG)) {
@@ -812,10 +812,10 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
812812
(dma_error & ETH_DMASR_TJTS)) {
813813
eth_stats_update_errors_tx(dev_data->iface);
814814
}
815-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
815+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
816816
break;
817817

818-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
818+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
819819
case HAL_ETH_ERROR_MAC:
820820
mac_error = HAL_ETH_GetMACError(heth);
821821

@@ -832,16 +832,16 @@ void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth)
832832
eth_stats_update_errors_tx(dev_data->iface);
833833
}
834834
break;
835-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
835+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
836836
}
837837

838-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
838+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
839839
dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRCRCEPR;
840840
dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRAEPR;
841841
#else
842842
dev_data->stats.error_details.rx_crc_errors = heth->Instance->MMCRFCECR;
843843
dev_data->stats.error_details.rx_align_errors = heth->Instance->MMCRFAECR;
844-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
844+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
845845

846846
#endif /* CONFIG_NET_STATISTICS_ETHERNET */
847847
}
@@ -959,11 +959,11 @@ static int eth_initialize(const struct device *dev)
959959
/* Enable timestamping of RX packets. We enable all packets to be
960960
* timestamped to cover both IEEE 1588 and gPTP.
961961
*/
962-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
962+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
963963
heth->Instance->MACTSCR |= ETH_MACTSCR_TSENALL;
964964
#else
965965
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSARFE;
966-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
966+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
967967
#endif /* CONFIG_PTP_CLOCK_STM32_HAL */
968968

969969
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
@@ -1052,13 +1052,13 @@ static void eth_stm32_mcast_filter(const struct device *dev, const struct ethern
10521052

10531053
__ASSERT_NO_MSG(hash_index < ARRAY_SIZE(dev_data->hash_index_cnt));
10541054

1055-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1055+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
10561056
hash_table[0] = heth->Instance->MACHT0R;
10571057
hash_table[1] = heth->Instance->MACHT1R;
10581058
#else
10591059
hash_table[0] = heth->Instance->MACHTLR;
10601060
hash_table[1] = heth->Instance->MACHTHR;
1061-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1061+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
10621062

10631063
if (filter->set) {
10641064
dev_data->hash_index_cnt[hash_index]++;
@@ -1075,13 +1075,13 @@ static void eth_stm32_mcast_filter(const struct device *dev, const struct ethern
10751075
}
10761076
}
10771077

1078-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1078+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
10791079
heth->Instance->MACHT0R = hash_table[0];
10801080
heth->Instance->MACHT1R = hash_table[1];
10811081
#else
10821082
heth->Instance->MACHTLR = hash_table[0];
10831083
heth->Instance->MACHTHR = hash_table[1];
1084-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1084+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
10851085
}
10861086

10871087
#endif /* CONFIG_ETH_STM32_MULTICAST_FILTER */
@@ -1196,7 +1196,7 @@ static int eth_stm32_hal_set_config(const struct device *dev,
11961196
break;
11971197
case ETHERNET_CONFIG_TYPE_PROMISC_MODE:
11981198
#if defined(CONFIG_NET_PROMISCUOUS_MODE)
1199-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1199+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
12001200
if (config->promisc_mode) {
12011201
heth->Instance->MACPFR |= ETH_MACPFR_PR;
12021202
} else {
@@ -1208,7 +1208,7 @@ static int eth_stm32_hal_set_config(const struct device *dev,
12081208
} else {
12091209
heth->Instance->MACFFR &= ~ETH_MACFFR_PM;
12101210
}
1211-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1211+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
12121212
ret = 0;
12131213
#endif /* CONFIG_NET_PROMISCUOUS_MODE */
12141214
break;
@@ -1330,7 +1330,7 @@ static int ptp_clock_stm32_set(const struct device *dev,
13301330

13311331
key = irq_lock();
13321332

1333-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1333+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
13341334
heth->Instance->MACSTSUR = tm->second;
13351335
heth->Instance->MACSTNUR = tm->nanosecond;
13361336
heth->Instance->MACTSCR |= ETH_MACTSCR_TSINIT;
@@ -1344,7 +1344,7 @@ static int ptp_clock_stm32_set(const struct device *dev,
13441344
while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSSTI_Msk) {
13451345
/* spin lock */
13461346
}
1347-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1347+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
13481348

13491349
irq_unlock(key);
13501350

@@ -1362,15 +1362,15 @@ static int ptp_clock_stm32_get(const struct device *dev,
13621362

13631363
key = irq_lock();
13641364

1365-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1365+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
13661366
tm->second = heth->Instance->MACSTSR;
13671367
tm->nanosecond = heth->Instance->MACSTNR;
13681368
second_2 = heth->Instance->MACSTSR;
13691369
#else
13701370
tm->second = heth->Instance->PTPTSHR;
13711371
tm->nanosecond = heth->Instance->PTPTSLR;
13721372
second_2 = heth->Instance->PTPTSHR;
1373-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1373+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
13741374

13751375
irq_unlock(key);
13761376

@@ -1398,7 +1398,7 @@ static int ptp_clock_stm32_adjust(const struct device *dev, int increment)
13981398
} else {
13991399
key = irq_lock();
14001400

1401-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1401+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
14021402
heth->Instance->MACSTSUR = 0;
14031403
if (increment >= 0) {
14041404
heth->Instance->MACSTNUR = increment;
@@ -1420,7 +1420,7 @@ static int ptp_clock_stm32_adjust(const struct device *dev, int increment)
14201420
while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSSTU_Msk) {
14211421
/* spin lock */
14221422
}
1423-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1423+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
14241424

14251425
ret = 0;
14261426
irq_unlock(key);
@@ -1459,7 +1459,7 @@ static int ptp_clock_stm32_rate_adjust(const struct device *dev, double ratio)
14591459
/* Update addend register */
14601460
addend_val = UINT32_MAX * (double)eth_dev_data->clk_ratio * ratio;
14611461

1462-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1462+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
14631463
heth->Instance->MACTSAR = addend_val;
14641464
heth->Instance->MACTSCR |= ETH_MACTSCR_TSADDREG;
14651465
while (heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG_Msk) {
@@ -1471,7 +1471,7 @@ static int ptp_clock_stm32_rate_adjust(const struct device *dev, double ratio)
14711471
while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU_Msk) {
14721472
/* spin lock */
14731473
}
1474-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1474+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
14751475

14761476
ret = 0;
14771477

@@ -1504,26 +1504,26 @@ static int ptp_stm32_init(const struct device *port)
15041504
ptp_context->eth_dev_data = eth_dev_data;
15051505

15061506
/* Mask the Timestamp Trigger interrupt */
1507-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1507+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
15081508
heth->Instance->MACIER &= ~(ETH_MACIER_TSIE);
15091509
#else
15101510
heth->Instance->MACIMR &= ~(ETH_MACIMR_TSTIM);
1511-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1511+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
15121512

15131513
/* Enable timestamping */
1514-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1514+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
15151515
heth->Instance->MACTSCR |= ETH_MACTSCR_TSENA;
15161516
#else
15171517
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSE;
1518-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1518+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
15191519

15201520
/* Query ethernet clock rate */
15211521
ret = clock_control_get_rate(eth_dev_data->clock,
1522-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1522+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
15231523
(clock_control_subsys_t)&eth_cfg->pclken,
15241524
#else
15251525
(clock_control_subsys_t)&eth_cfg->pclken_ptp,
1526-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1526+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
15271527
&ptp_hclk_rate);
15281528
if (ret) {
15291529
LOG_ERR("Failed to query ethernet clock");
@@ -1540,11 +1540,11 @@ static int ptp_stm32_init(const struct device *port)
15401540
LOG_ERR("PTP clock period is more than %d nanoseconds", UINT8_MAX);
15411541
return -EINVAL;
15421542
}
1543-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1543+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
15441544
heth->Instance->MACSSIR = ss_incr_ns << ETH_MACMACSSIR_SSINC_Pos;
15451545
#else
15461546
heth->Instance->PTPSSIR = ss_incr_ns;
1547-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1547+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
15481548

15491549
/* Program timestamp addend register */
15501550
eth_dev_data->clk_ratio =
@@ -1559,7 +1559,7 @@ static int ptp_stm32_init(const struct device *port)
15591559
eth_dev_data->clk_ratio_adj = 1.0f;
15601560
addend_val =
15611561
UINT32_MAX * eth_dev_data->clk_ratio * eth_dev_data->clk_ratio_adj;
1562-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1562+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
15631563
heth->Instance->MACTSAR = addend_val;
15641564
heth->Instance->MACTSCR |= ETH_MACTSCR_TSADDREG;
15651565
while (heth->Instance->MACTSCR & ETH_MACTSCR_TSADDREG_Msk) {
@@ -1571,24 +1571,24 @@ static int ptp_stm32_init(const struct device *port)
15711571
while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSARU_Msk) {
15721572
k_yield();
15731573
}
1574-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1574+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
15751575

15761576
/* Enable fine timestamp correction method */
1577-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1577+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
15781578
heth->Instance->MACTSCR |= ETH_MACTSCR_TSCFUPDT;
15791579
#else
15801580
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSFCU;
1581-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1581+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
15821582

15831583
/* Enable nanosecond rollover into a new second */
1584-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1584+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
15851585
heth->Instance->MACTSCR |= ETH_MACTSCR_TSCTRLSSR;
15861586
#else
15871587
heth->Instance->PTPTSCR |= ETH_PTPTSCR_TSSSR;
1588-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1588+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
15891589

15901590
/* Initialize timestamp */
1591-
#if defined(CONFIG_SOC_SERIES_STM32H7X) || defined(CONFIG_SOC_SERIES_STM32H5X)
1591+
#if DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet)
15921592
heth->Instance->MACSTSUR = 0;
15931593
heth->Instance->MACSTNUR = 0;
15941594
heth->Instance->MACTSCR |= ETH_MACTSCR_TSINIT;
@@ -1602,7 +1602,7 @@ static int ptp_stm32_init(const struct device *port)
16021602
while (heth->Instance->PTPTSCR & ETH_PTPTSCR_TSSTI_Msk) {
16031603
k_yield();
16041604
}
1605-
#endif /* CONFIG_SOC_SERIES_STM32H7X || CONFIG_SOC_SERIES_STM32H5X */
1605+
#endif /* DT_HAS_COMPAT_STATUS_OKAY(st_stm32h7_ethernet) */
16061606

16071607
#if defined(CONFIG_ETH_STM32_HAL_API_V2)
16081608
/* Set PTP Configuration done */

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