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aailletnashif
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soc: arm: reneas: Add r8a779f0 support
r8a779f0 SoC is part of the Renesas R-Car Gen4 SoC series. This SoC has a dual core lockstep Cortex-R52 CPU. Signed-off-by: Aymeric Aillet <[email protected]>
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# Copyright (c) 2023 IoT.bzh
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# SPDX-License-Identifier: Apache-2.0
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if SOC_R8A779F0
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config SOC
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default "r8a779f0"
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config NUM_IRQS
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default 1216 #960 SPI + 256 LPI
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config PINCTRL
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default y
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endif # SOC_R8A779F0
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# Renesas R-Car Gen4 SoC line
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# Copyright (c) 2023 IoT.bzh
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# SPDX-License-Identifier: Apache-2.0
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if SOC_SERIES_RCAR_GEN4
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source "soc/arm/renesas_rcar/gen4/Kconfig.defconfig.r8a779*"
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config SOC_SERIES
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default "gen4"
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endif # SOC_SERIES_RCAR_GEN4
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# Copyright (c) 2023 IoT.bzh
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# SPDX-License-Identifier: Apache-2.0
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config SOC_SERIES_RCAR_GEN4
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bool "Renesas R-Car Gen4 Cortex R52"
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select ARM
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select CPU_CORTEX_R52
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select GIC_SINGLE_SECURITY_STATE
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select SOC_FAMILY_RCAR
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select CLOCK_CONTROL_RCAR_CPG_MSSR if CLOCK_CONTROL
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select ARM_ARCH_TIMER
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help
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Enable support for Renesas R-Car Gen4 SoC series
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# Copyright (c) 2023 IoT.bzh
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# SPDX-License-Identifier: Apache-2.0
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choice
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prompt "Renesas RCar SoC Selection"
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depends on SOC_SERIES_RCAR_GEN4
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config SOC_R8A779F0
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bool "r8a779f0"
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endchoice
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/*
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* Copyright (c) 2023 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <zephyr/arch/arm/cortex_a_r/scripts/linker.ld>

soc/arm/renesas_rcar/gen4/soc.h

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/*
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* Copyright (c) 2023 IoT.bzh
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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/* Define CMSIS configurations */
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#define __CR_REV 1U
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/* Do not let CMSIS to handle GIC and Timer */
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#define __GIC_PRESENT 0
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#define __TIM_PRESENT 0
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#endif /* _SOC__H_ */

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