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soc: espressif: add region description for rtc ram memory
Adds separate memory regions for rtc ram memory areas and reworks linker scripts to make use of their starting addresses and lengths Signed-off-by: Marcio Ribeiro <[email protected]>
1 parent e57676a commit f23316c

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14 files changed

+123
-23
lines changed

14 files changed

+123
-23
lines changed

‎dts/riscv/espressif/esp32c3/esp32c3_common.dtsi‎

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -100,6 +100,12 @@
100100
zephyr,memory-region = "SRAM1";
101101
};
102102

103+
rtc_fast_ram: memory@50000000 {
104+
compatible = "zephyr,memory-region", "mmio-sram";
105+
reg = <0x50000000 DT_SIZE_K(8)>;
106+
zephyr,memory-region = "RTC_FAST_RAM";
107+
};
108+
103109
intc: interrupt-controller@600c2000 {
104110
compatible = "espressif,esp32-intc";
105111
#address-cells = <0>;

‎dts/xtensa/espressif/esp32/esp32_common.dtsi‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -138,6 +138,18 @@
138138
};
139139
};
140140

141+
rtc_fast_ram: memory@3ff80000 {
142+
compatible = "zephyr,memory-region", "mmio-sram";
143+
reg = <0x3ff80000 DT_SIZE_K(8)>;
144+
zephyr,memory-region = "RTC_FAST_RAM";
145+
};
146+
147+
rtc_slow_ram: memory@50000000 {
148+
compatible = "zephyr,memory-region", "mmio-sram";
149+
reg = <0x50000000 DT_SIZE_K(8)>;
150+
zephyr,memory-region = "RTC_SLOW_RAM";
151+
};
152+
141153
icache0: icache0@400d0000 {
142154
compatible = "zephyr,memory-region", "mmio-sram";
143155
reg = <0x400d0000 DT_SIZE_K(11456)>;

‎dts/xtensa/espressif/esp32s2/esp32s2_common.dtsi‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -116,6 +116,18 @@
116116
};
117117
};
118118

119+
rtc_fast_ram: memory@3ff9e000 {
120+
compatible = "zephyr,memory-region", "mmio-sram";
121+
reg = <0x3ff9e000 DT_SIZE_K(8)>;
122+
zephyr,memory-region = "RTC_FAST_RAM";
123+
};
124+
125+
rtc_slow_ram: memory@50000000 {
126+
compatible = "zephyr,memory-region", "mmio-sram";
127+
reg = <0x50000000 DT_SIZE_K(8)>;
128+
zephyr,memory-region = "RTC_SLOW_RAM";
129+
};
130+
119131
icache0: icache0@40080000 {
120132
compatible = "zephyr,memory-region";
121133
reg = <0x40080000 DT_SIZE_K(7680)>;

‎dts/xtensa/espressif/esp32s3/esp32s3_common.dtsi‎

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -161,6 +161,18 @@
161161
#mbox-cells = <1>;
162162
};
163163

164+
rtc_slow_ram: memory@50000000 {
165+
compatible = "zephyr,memory-region", "mmio-sram";
166+
reg = <0x50000000 DT_SIZE_K(8)>;
167+
zephyr,memory-region = "RTC_SLOW_RAM";
168+
};
169+
170+
rtc_fast_ram: memory@600fe000 {
171+
compatible = "zephyr,memory-region", "mmio-sram";
172+
reg = <0x600fe000 DT_SIZE_K(8)>;
173+
zephyr,memory-region = "RTC_FAST_RAM";
174+
};
175+
164176
intc: interrupt-controller@600c2000 {
165177
#interrupt-cells = <3>;
166178
#address-cells = <0>;

‎soc/espressif/esp32/default.ld‎

Lines changed: 12 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -34,6 +34,14 @@ procpu_ext_ram_org = DCACHE1_START;
3434
procpu_ext_ram_len = DCACHE1_SIZE;
3535
#endif
3636

37+
/* RTC RAM memory segments */
38+
rtc_slow_org = RCT_SLOW_RAM_START;
39+
rtc_slow_len = RCT_SLOW_RAM_SIZE;
40+
rtc_data_org = RCT_FAST_RAM_START;
41+
rtc_data_len = RCT_FAST_RAM_SIZE;
42+
rtc_iram_org = RCT_FAST_RAM_START + 0x140000;
43+
rtc_iram_len = RCT_FAST_RAM_SIZE;
44+
3745
/* Aliases */
3846
#define FLASH_CODE_REGION irom0_0_seg
3947
#define RODATA_REGION drom0_0_seg
@@ -87,9 +95,9 @@ MEMORY
8795
irom0_0_seg(RX): org = procpu_irom_org, len = procpu_irom_len
8896
drom0_0_seg(R): org = procpu_drom_org, len = procpu_drom_len
8997

90-
rtc_iram_seg(RWX): org = 0x400c0000, len = 0x2000
91-
rtc_slow_seg(RW): org = 0x50000000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
92-
rtc_data_seg(RW): org = 0x3ff80000, len = 0x2000
98+
rtc_iram_seg(RWX): org = rtc_iram_org, len = rtc_iram_len
99+
rtc_slow_seg(RW): org = rtc_slow_org, len = rtc_slow_len - CONFIG_RESERVE_RTC_MEM
100+
rtc_data_seg(RW): org = rtc_data_org, len = rtc_data_len
93101

94102
/* We reduced the size of rtc_slow_seg by CONFIG_RESERVE_RTC_MEM value.
95103
* It reserves the amount of RTC slow memory that we use for this memory segment.
@@ -98,7 +106,7 @@ MEMORY
98106
* org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM
99107
*/
100108
#if (CONFIG_RESERVE_RTC_MEM > 0)
101-
rtc_slow_reserved_seg(RW): org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
109+
rtc_slow_reserved_seg(RW): org = rtc_slow_org + rtc_slow_len - CONFIG_RESERVE_RTC_MEM,
102110
len = CONFIG_RESERVE_RTC_MEM
103111
#endif
104112

‎soc/espressif/esp32/memory.h‎

Lines changed: 8 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -26,6 +26,14 @@
2626
#define SRAM2_DRAM_USER_START (SRAM2_DRAM_START + SRAM2_DRAM_SHM_SIZE)
2727
#define SRAM2_DRAM_USER_SIZE (SRAM2_DRAM_END - SRAM2_DRAM_USER_START)
2828

29+
/* RTC SLOW RAM (8kB) */
30+
#define RCT_SLOW_RAM_START DT_REG_ADDR(DT_NODELABEL(rtc_slow_ram))
31+
#define RCT_SLOW_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(rtc_slow_ram))
32+
33+
/* RTC FAST RAM (8kB) */
34+
#define RCT_FAST_RAM_START DT_REG_ADDR(DT_NODELABEL(rtc_fast_ram))
35+
#define RCT_FAST_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(rtc_fast_ram))
36+
2937
/** Simplified memory map for the bootloader.
3038
* Make sure the bootloader can load into main memory without overwriting itself.
3139
*

‎soc/espressif/esp32c3/default.ld‎

Lines changed: 6 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -28,6 +28,10 @@ user_idram_size = (user_dram_end - user_dram_seg_org);
2828
user_iram_seg_len = user_idram_size;
2929
user_dram_seg_len = user_idram_size;
3030

31+
/* RTC RAM memory segment */
32+
rtc_iram_org = RCT_FAST_RAM_START;
33+
rtc_iram_len = RCT_FAST_RAM_SIZE;
34+
3135
/* Aliases */
3236
#define FLASH_CODE_REGION irom0_0_seg
3337
#define RODATA_REGION drom0_0_seg
@@ -73,7 +77,7 @@ MEMORY
7377
irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
7478
drom0_0_seg (R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
7579

76-
rtc_iram_seg(RWX): org = 0x50000000, len = 0x2000 - CONFIG_RESERVE_RTC_MEM
80+
rtc_iram_seg(RWX): org = rtc_iram_org, len = rtc_iram_len - CONFIG_RESERVE_RTC_MEM
7781

7882
/* We reduced the size of rtc_iram_seg by CONFIG_RESERVE_RTC_MEM value.
7983
It reserves the amount of RTC fast memory that we use for this memory segment.
@@ -82,7 +86,7 @@ MEMORY
8286
The aim of this is to keep data that will not be moved around and have a fixed address.
8387
*/
8488
#if (CONFIG_RESERVE_RTC_MEM > 0)
85-
rtc_reserved_seg(RW): org = 0x50000000 + 0x2000 - CONFIG_RESERVE_RTC_MEM,
89+
rtc_reserved_seg(RW): org = rtc_iram_org + rtc_iram_len - CONFIG_RESERVE_RTC_MEM,
8690
len = CONFIG_RESERVE_RTC_MEM
8791
#endif
8892

‎soc/espressif/esp32c3/memory.h‎

Lines changed: 3 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -13,6 +13,9 @@
1313
#define SRAM1_SIZE DT_REG_SIZE(DT_NODELABEL(sram1))
1414
/* ICache size is fixed to 16KB on ESP32-C3 */
1515
#define ICACHE_SIZE SRAM0_SIZE
16+
/* RTC FAST RAM (8kB) */
17+
#define RCT_FAST_RAM_START DT_REG_ADDR(DT_NODELABEL(rtc_fast_ram))
18+
#define RCT_FAST_RAM_SIZE DT_REG_SIZE(DT_NODELABEL(rtc_fast_ram))
1619

1720
/** Simplified memory map for the bootloader.
1821
* Make sure the bootloader can load into main memory without overwriting itself.

‎soc/espressif/esp32c6/default.ld‎

Lines changed: 11 additions & 6 deletions
Original file line numberDiff line numberDiff line change
@@ -68,11 +68,11 @@ MEMORY
6868
drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
6969

7070
#if CONFIG_ULP_COPROC_ENABLED
71-
lp_ram_seg(RW): org = LPSRAM_IRAM_START + ULP_COPROC_RESERVE_MEM,
72-
len = LPSRAM_SIZE - ULP_COPROC_RESERVE_MEM - CONFIG_RESERVE_RTC_MEM
71+
lp_ram_seg(RW): org = LPSRAM_IRAM_START + ULP_COPROC_RESERVE_MEM,
72+
len = LPSRAM_SIZE - ULP_COPROC_RESERVE_MEM - CONFIG_RESERVE_RTC_MEM
7373
#else
74-
lp_ram_seg(RW): org = LPSRAM_IRAM_START,
75-
len = 0x4000 - CONFIG_RESERVE_RTC_MEM
74+
lp_ram_seg(RW): org = LPSRAM_IRAM_START,
75+
len = LPSRAM_SIZE - CONFIG_RESERVE_RTC_MEM
7676
#endif
7777
/* We reduced the size of lp_ram_seg by CONFIG_RESERVE_RTC_MEM value.
7878
It reserves the amount of LP memory that we use for this memory segment.
@@ -82,8 +82,13 @@ MEMORY
8282
The aim of this is to keep data that will not be moved around and have a fixed address.
8383
*/
8484
#if (CONFIG_RESERVE_RTC_MEM > 0)
85-
lp_reserved_seg(RW) : org = LPSRAM_IRAM_START + 0x4000 - CONFIG_RESERVE_RTC_MEM,
86-
len = CONFIG_RESERVE_RTC_MEM
85+
#if CONFIG_ULP_COPROC_ENABLED
86+
lp_reserved_seg(RW): org = LPSRAM_IRAM_START + LPSRAM_SIZE - ULP_COPROC_RESERVE_MEM - CONFIG_RESERVE_RTC_MEM,
87+
len = CONFIG_RESERVE_RTC_MEM
88+
#else
89+
lp_reserved_seg(RW): org = LPSRAM_IRAM_START + LPSRAM_SIZE - CONFIG_RESERVE_RTC_MEM,
90+
len = CONFIG_RESERVE_RTC_MEM
91+
#endif
8792
#endif
8893

8994
#ifdef CONFIG_GEN_ISR_TABLES

‎soc/espressif/esp32h2/default.ld‎

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -67,8 +67,8 @@ MEMORY
6767
irom0_0_seg(RX): org = IROM_SEG_ORG, len = IROM_SEG_LEN
6868
drom0_0_seg(R): org = DROM_SEG_ORG, len = DROM_SEG_LEN
6969

70-
lp_ram_seg(RW): org = LPSRAM_IRAM_START,
71-
len = LPSRAM_SIZE - CONFIG_RESERVE_RTC_MEM
70+
lp_ram_seg(RW): org = LPSRAM_IRAM_START,
71+
len = LPSRAM_SIZE - CONFIG_RESERVE_RTC_MEM
7272

7373
/* We reduced the size of lp_ram_seg by CONFIG_RESERVE_RTC_MEM value.
7474
It reserves the amount of LP memory that we use for this memory segment.
@@ -78,8 +78,8 @@ MEMORY
7878
The aim of this is to keep data that will not be moved around and have a fixed address.
7979
*/
8080
#if (CONFIG_RESERVE_RTC_MEM > 0)
81-
lp_reserved_seg(RW) : org = LPSRAM_IRAM_START + LPSRAM_SIZE - CONFIG_RESERVE_RTC_MEM,
82-
len = CONFIG_RESERVE_RTC_MEM
81+
lp_reserved_seg(RW): org = LPSRAM_IRAM_START + LPSRAM_SIZE - CONFIG_RESERVE_RTC_MEM,
82+
len = CONFIG_RESERVE_RTC_MEM
8383
#endif
8484

8585
#ifdef CONFIG_GEN_ISR_TABLES

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