drivers: clock_control: stm32g0 soc enables the PWR clock

FRASTM · MaureenHelm · commit f3c681166b67 · 2021-01-06T08:09:47.000-06:00
After system reset, the PWR interface clock must be enabled
by setting the PWREN bit of the RCC_APBENR1
This sequence is needed to use the RTC.

Signed-off-by: Francois Ramu &lt;francois.ramu@st.com&gt;
diff --git a/drivers/clock_control/clock_stm32g0.c b/drivers/clock_control/clock_stm32g0.c
@@ -42,7 +42,8 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)
  */
 void config_enable_default_clocks(void)
 {
-	/* Do nothing */
+	/* Enable the power interface clock */
+	LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);
 }
 
 /**

Original file line number	Diff line number	Diff line change
`@@ -42,7 +42,8 @@ void config_pll_init(LL_UTILS_PLLInitTypeDef *pllinit)`
`42`	`42`	`*/`
`43`	`43`	`void config_enable_default_clocks(void)`
`44`	`44`	`{`
`45`		`- /* Do nothing */`
	`45`	`+ /* Enable the power interface clock */`
	`46`	`+ LL_APB1_GRP1_EnableClock(LL_APB1_GRP1_PERIPH_PWR);`
`46`	`47`	`}`
`47`	`48`
`48`	`49`	`/**`