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soc: adi: Add the MAX78002 SoC
Added MAX78002 Kconfig and dts files. Signed-off-by: Furkan Akkiz <[email protected]>
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‎dts/arm/adi/max32/max78002-pinctrl.dtsi‎

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‎dts/arm/adi/max32/max78002.dtsi‎

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/*
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* Copyright (c) 2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arm/armv7-m.dtsi>
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#include <adi/max32/max32xxx.dtsi>
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#include <zephyr/dt-bindings/dma/max78002_dma.h>
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&clk_ipo {
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clock-frequency = <DT_FREQ_M(120)>;
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};
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&clk_inro {
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clock-frequency = <DT_FREQ_K(30)>;
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};
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/delete-node/ &clk_erfo;
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/* MAX78002 extra clocks. */
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/ {
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clocks {
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clk_ipll: clk_ipll {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(100)>;
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status = "disabled";
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};
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clk_ebo: clk_ebo {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <DT_FREQ_M(25)>;
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status = "disabled";
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};
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};
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};
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&flash0 {
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reg = <0x10000000 DT_SIZE_K(2560)>;
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erase-block-size = <16384>;
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};
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&pinctrl {
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reg = <0x40008000 0x2200>;
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gpio2: gpio@40080400 {
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reg = <0x40080400 0x200>;
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compatible = "adi,max32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <26 0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 0>;
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status = "disabled";
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};
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gpio3: gpio@40080600 {
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reg = <0x40080600 0x200>; // Address and size are dummy.
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compatible = "adi,max32-gpio";
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gpio-controller;
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#gpio-cells = <2>;
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interrupts = <54 0>;
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status = "disabled";
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};
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};
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&adc {
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compatible = "adi,max32-adc-sar", "adi,max32-adc";
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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clock-divider = <16>;
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channel-count = <17>;
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track-count = <4>;
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idle-count = <0>;
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vref-mv = <1250>;
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resolution = <12>;
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};
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/* MAX78002 extra peripherals. */
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/ {
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soc {
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sram1: memory@20008000 {
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compatible = "mmio-sram";
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reg = <0x20008000 DT_SIZE_K(32)>;
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};
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sram2: memory@20010000 {
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compatible = "mmio-sram";
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reg = <0x20010000 DT_SIZE_K(64)>;
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};
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sram3: memory@20020000 {
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compatible = "mmio-sram";
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reg = <0x20020000 DT_SIZE_K(64)>;
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};
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sram4: memory@20030000 {
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compatible = "mmio-sram";
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reg = <0x20030000 DT_SIZE_K(64)>;
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};
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sram5: memory@20040000 {
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compatible = "mmio-sram";
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reg = <0x20040000 DT_SIZE_K(64)>;
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};
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sram6: memory@20050000 {
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compatible = "mmio-sram";
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reg = <0x20050000 DT_SIZE_K(48)>;
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};
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sram7: memory@2005c000 {
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compatible = "mmio-sram";
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reg = <0x2005c000 DT_SIZE_K(16)>;
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};
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uart3: serial@40081400 {
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compatible = "adi,max32-uart";
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reg = <0x40081400 0x400>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 4>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
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interrupts = <88 0>;
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status = "disabled";
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};
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spi0: spi@400be000 {
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compatible = "adi,max32-spi";
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reg = <0x400be000 0x1000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 16>;
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interrupts = <56 0>;
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status = "disabled";
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};
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spi1: spi@40046000 {
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compatible = "adi,max32-spi";
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reg = <0x40046000 0x2000>;
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#address-cells = <1>;
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#size-cells = <0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 6>;
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interrupts = <16 0>;
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status = "disabled";
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};
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dma0: dma@40028000 {
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compatible = "adi,max32-dma";
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reg = <0x40028000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS0 5>;
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interrupts = <28 0>, <29 0>, <30 0>, <31 0>;
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dma-channels = <4>;
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status = "disabled";
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#dma-cells = <2>;
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};
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wdt1: watchdog@40080800 {
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compatible = "adi,max32-watchdog";
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reg = <0x40080800 0x400>;
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interrupts = <57 0>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 1>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_PCLK>;
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status = "disabled";
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};
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lptimer0: timer@40080c00 {
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compatible = "adi,max32-timer";
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reg = <0x40080c00 0x400>;
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interrupts = <9 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 2>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
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prescaler = <1>;
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pwm {
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compatible = "adi,max32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "adi,max32-counter";
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status = "disabled";
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};
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};
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lptimer1: timer@40081000 {
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compatible = "adi,max32-timer";
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reg = <0x40081000 0x400>;
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interrupts = <10 0>;
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status = "disabled";
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clocks = <&gcr ADI_MAX32_CLOCK_BUS2 3>;
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clock-source = <ADI_MAX32_PRPH_CLK_SRC_IBRO>;
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prescaler = <1>;
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pwm {
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compatible = "adi,max32-pwm";
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status = "disabled";
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#pwm-cells = <3>;
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};
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counter {
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compatible = "adi,max32-counter";
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status = "disabled";
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};
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};
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w1: w1@4003d000 {
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compatible = "adi,max32-w1";
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reg = <0x4003d000 0x1000>;
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clocks = <&gcr ADI_MAX32_CLOCK_BUS1 13>;
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interrupts = <67 0>;
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status = "disabled";
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};
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};
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};

‎soc/adi/max32/CMakeLists.txt‎

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zephyr_sources(soc.c)
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zephyr_linker_sources_ifdef(CONFIG_SOC_FLASH_MAX32 SECTIONS flash.ld)
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zephyr_linker_sources_ifdef(CONFIG_SOC_MAX78002 SECTIONS max78002.ld)
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set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

‎soc/adi/max32/Kconfig‎

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config SOC_MAX32690
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select CPU_CORTEX_M4
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config SOC_MAX78002_M4
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select CPU_CORTEX_M4
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if SOC_FAMILY_MAX32
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config MAX32_ON_ENTER_CPU_IDLE_HOOK

‎soc/adi/max32/Kconfig.defconfig‎

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if SOC_FAMILY_MAX32
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8-
rsource "Kconfig.defconfig.max32*"
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rsource "Kconfig.defconfig.max*"
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config SRAM_VECTOR_TABLE
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default y

‎soc/adi/max32/Kconfig.defconfig.max78002‎

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# Analog Devices MAX78002 MCU
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# Copyright (c) 2024 Analog Devices, Inc.
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# SPDX-License-Identifier: Apache-2.0
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if SOC_MAX78002
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/clocks/clk_ipo,clock-frequency)
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config NUM_IRQS
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default 105
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endif # SOC_MAX78002

‎soc/adi/max32/Kconfig.soc‎

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bool
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select SOC_MAX32690
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config SOC_MAX78002
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bool
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select SOC_FAMILY_MAX32
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config SOC_MAX78002_M4
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bool
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select SOC_MAX78002
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config SOC
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default "max32655" if SOC_MAX32655
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default "max32662" if SOC_MAX32662
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default "max32675" if SOC_MAX32675
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default "max32680" if SOC_MAX32680
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default "max32690" if SOC_MAX32690
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default "max78002" if SOC_MAX78002

‎soc/adi/max32/max78002.ld‎

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/*
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* Copyright (c) 2024 Analog Devices, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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SECTION_PROLOGUE(.shared,, SUBALIGN(4))
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{
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_shared = .;
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*(.mailbox*)
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*(.shared*)
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_eshared = .;
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} GROUP_DATA_LINK_IN(RAMABLE_REGION, ROMABLE_REGION)

‎soc/adi/max32/soc.yml‎

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- name: max32690
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cpuclusters:
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- name: m4
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- name: max78002
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cpuclusters:
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- name: m4

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