arch: arm: nxp: imxrt1015: add device support

- Add SoC information for RT1015

Signed-off-by: Ryan QIAN <[email protected]>

Author: jhqian

soc/arm/nxp_imx/rt/Kconfig.defconfig.mimxrt1015

@@ -0,0 +1,29 @@
+# Kconfig - i.MX RT1015
+#
+# Copyright (c) 2019, NXP
+#
+# SPDX-License-Identifier: Apache-2.0
+#
+
+if SOC_MIMXRT1015
+
+config SOC
+	string
+	default "mimxrt1015"
+
+config NUM_IRQS
+	default 142
+
+config ARM_DIV
+	default 0
+
+config AHB_DIV
+	default 0
+
+config IPG_DIV
+	default 3
+
+config GPIO
+	default y
+
+endif # SOC_MIMXRT1015

soc/arm/nxp_imx/rt/Kconfig.soc

@@ -9,6 +9,22 @@ choice
 prompt "i.MX RT Selection"
 depends on SOC_SERIES_IMX_RT
 
+config SOC_MIMXRT1015
+	bool "SOC_MIMXRT1015"
+	select HAS_MCUX
+	select HAS_MCUX_CACHE
+	select HAS_MCUX_CCM
+	select HAS_MCUX_IGPIO
+	select HAS_MCUX_LPI2C
+	select HAS_MCUX_LPSPI
+	select HAS_MCUX_LPUART
+	select HAS_MCUX_TRNG
+	select CPU_HAS_FPU_DOUBLE_PRECISION
+	select CPU_HAS_ARM_MPU
+	select INIT_SYS_PLL
+	select INIT_USB1_PLL
+	select INIT_ENET_PLL
+
 config SOC_MIMXRT1021
 	bool "SOC_MIMXRT1021"
 	select HAS_MCUX
@@ -117,6 +133,12 @@ endchoice
 
 if SOC_SERIES_IMX_RT
 
+config SOC_PART_NUMBER_MIMXRT1015CAF4A
+	bool
+
+config SOC_PART_NUMBER_MIMXRT1015DAF5A
+	bool
+
 config SOC_PART_NUMBER_MIMXRT1021CAF4A
 	bool
 
@@ -173,6 +195,8 @@ config SOC_PART_NUMBER_MIMXRT1064DVL6A
 
 config SOC_PART_NUMBER_IMX_RT
 	string
+	default "MIMXRT1015CAF4A" if SOC_PART_NUMBER_MIMXRT1015CAF4A
+	default "MIMXRT1015DAF5A" if SOC_PART_NUMBER_MIMXRT1015DAF5A
 	default "MIMXRT1021CAF4A" if SOC_PART_NUMBER_MIMXRT1021CAF4A
 	default "MIMXRT1021CAG4A" if SOC_PART_NUMBER_MIMXRT1021CAG4A
 	default "MIMXRT1021DAF5A" if SOC_PART_NUMBER_MIMXRT1021DAF5A

soc/arm/nxp_imx/rt/arm_mpu_mem_cfg.h

@@ -26,6 +26,8 @@
 #define REGION_FLASH_SIZE REGION_4M
 #elif CONFIG_FLASH_SIZE == 8192
 #define REGION_FLASH_SIZE REGION_8M
+#elif CONFIG_FLASH_SIZE == 16384
+#define REGION_FLASH_SIZE REGION_16M
 #elif CONFIG_FLASH_SIZE == 65536
 #define REGION_FLASH_SIZE REGION_64M
 #else

soc/arm/nxp_imx/rt/soc.c

@@ -38,7 +38,7 @@ const clock_usb_pll_config_t usb1PllConfig = {
 #ifdef CONFIG_INIT_ENET_PLL
 /* ENET PLL configuration for RUN mode */
 const clock_enet_pll_config_t ethPllConfig = {
-#ifdef CONFIG_SOC_MIMXRT1021
+#if defined(CONFIG_SOC_MIMXRT1021) || defined(CONFIG_SOC_MIMXRT1015)
 	.enableClkOutput500M = true,
 #endif
 #ifdef CONFIG_ETH_MCUX