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galaknashif
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dts: Cleanup litex,clk binding
Rework the litex,clk to use the clock-controller.yaml and remove address-cells/size-cells as they aren't needed for the binding. Signed-off-by: Kumar Gala <[email protected]>
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dts/bindings/clock/litex,clk.yaml

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# Copyright (c) 2020 Antmicro <www.antmicro.com>
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# SPDX-License-Identifier: Apache-2.0
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include: base.yaml
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include: [clock-controller.yaml, base.yaml]
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description: |
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LiteX Mixed Mode Clock Manager
@@ -21,28 +21,8 @@ properties:
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"#clock-cells":
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required: true
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type: int
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description: |
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Number of cells in a clock specifier;
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Typically 0 for nodes with a single clock output
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and 1 for nodes with multiple clock outputs.
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const: 1
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"#address-cells":
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required: true
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type: int
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description: |
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Number of cells that are needed to form the base address
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part in the reg property.
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default: 1
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"#size-cells":
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required: true
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type: int
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description: |
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Used to state how many cells are in each field of a reg property
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default: 0
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clock-output-names:
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required: true
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type: string-array

dts/riscv/riscv32-litex-vexriscv.dtsi

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"drp_dat_w",
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"drp_dat_r";
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#clock-cells = <1>;
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#address-cells = <1>;
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#size-cells = <1>;
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clocks = <&clk0 0>, <&clk1 1>;
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clock-output-names = "CLK_0", "CLK_1";
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litex,lock-timeout = <10>;

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