dts: Cleanup litex,clk binding

Rework the litex,clk to use the clock-controller.yaml and remove
address-cells/size-cells as they aren't needed for the binding.

Signed-off-by: Kumar Gala <[email protected]>

Author: galak

dts/bindings/clock/litex,clk.yaml

@@ -1,7 +1,7 @@
 # Copyright (c) 2020 Antmicro <www.antmicro.com>
 # SPDX-License-Identifier: Apache-2.0
 
-include: base.yaml
+include: [clock-controller.yaml, base.yaml]
 
 description: |
   LiteX Mixed Mode Clock Manager
@@ -21,28 +21,8 @@ properties:
 
   "#clock-cells":
     required: true
-    type: int
-    description: |
-      Number of cells in a clock specifier;
-      Typically 0 for nodes with a single clock output
-      and 1 for nodes with multiple clock outputs.
     const: 1
 
-  "#address-cells":
-    required: true
-    type: int
-    description: |
-      Number of cells that are needed to form the base address
-      part in the reg property.
-    default: 1
-
-  "#size-cells":
-    required: true
-    type: int
-    description: |
-      Used to state how many cells are in each field of a reg property
-    default: 0
-
   clock-output-names:
     required: true
     type: string-array

dts/riscv/riscv32-litex-vexriscv.dtsi

@@ -211,8 +211,6 @@
 				    "drp_dat_w",
 				    "drp_dat_r";
 			#clock-cells = <1>;
-			#address-cells = <1>;
-			#size-cells = <1>;
 			clocks = <&clk0 0>, <&clk1 1>;
 			clock-output-names = "CLK_0", "CLK_1";
 			litex,lock-timeout = <10>;