dts: renesas: rx: Initial support dts SoC layer on RX26T.

This commit to initial support dts SoC layer on RX26T

Signed-off-by: Hau Ho <[email protected]>

Author: Hau Ho

dts/rx/renesas/r5f526tfddfp.dtsi

@@ -0,0 +1,181 @@
+/*
+ * Copyright (c) 2025 Renesas Electronics Corporation
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <rx/renesas/rx26t-common.dtsi>
+#include <freq.h>
+#include <zephyr/dt-bindings/clock/rx_clock.h>
+
+/ {
+	clocks: clocks {
+		#address-cells = <1>;
+		#size-cells = <1>;
+
+		xtal: clock-main-osc {
+			compatible = "renesas,rx-cgc-root-clock";
+			clock-frequency = <DT_FREQ_M(10)>;
+			mosel = <0>;
+			stabilization-time = <4>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		hoco: clock-hoco {
+			compatible = "renesas,rx-cgc-root-clock";
+			clock-frequency = <DT_FREQ_M(16)>;
+			#clock-cells = <0>;
+			status = "okay";
+		};
+
+		loco: clock-loco {
+			compatible = "renesas,rx-cgc-root-clock";
+			clock-frequency =  <240000>;
+			#clock-cells = <0>;
+			status = "okay";
+		};
+
+		iwdtlsclk: clock-iwdt-low-speed {
+			compatible = "renesas,rx-cgc-root-clock";
+			clock-frequency = <120000>;
+			#clock-cells = <0>;
+			status = "disabled";
+		};
+
+		pll: pll {
+			compatible = "renesas,rx-cgc-pll";
+			#clock-cells = <0>;
+			div = <1>;
+			clocks = <&xtal>;
+			mul = <RX_PLL_MUL_24>;
+			status = "disabled";
+		};
+
+		canfdmclk: clock-canfdm {
+			compatible = "renesas,rx-cgc-root-clock";
+			clock-frequency = <DT_FREQ_M(24)>;
+			#clock-cells = <0>;
+			status = "okay";
+		};
+
+		pclkblock: pclkblock@80010 {
+			compatible = "renesas,rx-cgc-pclk-block";
+			reg = <0x00080010 4>, <0x00080014 4>, <0x00080018 4>,
+					<0x0008001C 4>;
+			reg-names = "MSTPA", "MSTPB", "MSTPC", "MSTPD";
+			#clock-cells = <0>;
+			clocks = <&pll>;
+			status = "okay";
+
+			iclk: iclk {
+				compatible = "renesas,rx-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			fclk: fclk {
+				compatible = "renesas,rx-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclka: pclka {
+				compatible = "renesas,rx-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkb: pclkb {
+				compatible = "renesas,rx-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkc: pclkc {
+				compatible = "renesas,rx-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			pclkd: pclkd {
+				compatible = "renesas,rx-cgc-pclk";
+				div = <4>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+
+			canfdclk: clock-canfd {
+				compatible = "renesas,rx-cgc-pclk";
+				div = <2>;
+				#clock-cells = <2>;
+				status = "okay";
+			};
+		};
+
+		caclclk: caclclk {
+			compatible = "renesas,rx-cgc-pclk";
+			clocks = <&loco>;
+			#clock-cells = <2>;
+			status = "disabled";
+		};
+
+		cacmclk: cacmclk {
+			compatible = "renesas,rx-cgc-pclk";
+			clocks = <&xtal>;
+			#clock-cells = <2>;
+			status = "disabled";
+		};
+
+		cachclk: cachclk {
+			compatible = "renesas,rx-cgc-pclk";
+			clocks = <&hoco>;
+			#clock-cells = <2>;
+			status = "disabled";
+		};
+
+		caciclk: caciclk {
+			compatible = "renesas,rx-cgc-pclk";
+			clocks = <&iwdtlsclk>;
+			#clock-cells = <2>;
+			status = "disabled";
+		};
+
+		iwdtclk: iwdtclk {
+			compatible = "renesas,rx-cgc-pclk";
+			clocks = <&iwdtlsclk>;
+			#clock-cells = <2>;
+			status = "disabled";
+		};
+	};
+
+	soc {
+		sram0: memory@0 {
+			device_type = "memory";
+			compatible = "mmio-sram";
+			reg = <0x0 DT_SIZE_K(64)>;
+		};
+
+		flash: flash-controller@7e0000 {
+			#address-cells = <1>;
+			#size-cells = <1>;
+			compatible = "renesas,rx-flash";
+			reg = <0x007e0000 0x1000>;
+
+			code_flash: flash@fff80000 {
+				compatible = "renesas,rx-nv-flash";
+				reg = <0xfff80000 DT_SIZE_K(512)>;
+			};
+
+			data_flash: flash@100000 {
+				compatible = "renesas,rx-nv-flash";
+				reg = <0x00100000 DT_SIZE_K(16)>;
+			};
+		};
+	};
+};