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drivers/espi: ite: Make ITE's eSPI driver to support PVT2 and PVT3
Make ITE's eSPI driver to support PVT2 and PVT3, but it is not enabled by default. Signed-off-by: Tim Lin <[email protected]>
1 parent fff5d4c commit f4e466e

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6 files changed

+170
-8
lines changed

6 files changed

+170
-8
lines changed

‎drivers/espi/Kconfig.it8xxx2

Lines changed: 0 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -23,9 +23,6 @@ config ESPI_PERIPHERAL_HOST_IO
2323
config ESPI_PERIPHERAL_HOST_IO_PVT
2424
default y
2525

26-
config ESPI_PERIPHERAL_HOST_IO_PVT_PORT_NUM
27-
default 0x0068
28-
2926
config ESPI_PERIPHERAL_DEBUG_PORT_80
3027
default y
3128

‎drivers/espi/espi_it8xxx2.c

Lines changed: 160 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -33,6 +33,8 @@ LOG_MODULE_REGISTER(espi, CONFIG_ESPI_LOG_LEVEL);
3333
#define IT8XXX2_PMC2_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 6, irq)
3434
#define IT8XXX2_TRANS_IRQ DT_INST_IRQ_BY_IDX(0, 7, irq)
3535
#define IT8XXX2_PMC3_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 8, irq)
36+
#define IT8XXX2_PMC4_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 9, irq)
37+
#define IT8XXX2_PMC5_IBF_IRQ DT_INST_IRQ_BY_IDX(0, 10, irq)
3638

3739
/* General Capabilities and Configuration 1 */
3840
#define IT8XXX2_ESPI_MAX_FREQ_MASK GENMASK(2, 0)
@@ -319,8 +321,36 @@ struct pmc_regs {
319321
volatile uint8_t PM3IC;
320322
/* 0x25: Host Interface PM Channel 3 Interrupt Enable */
321323
volatile uint8_t PM3IE;
322-
/* 0x26-0xff: Reserved3 */
323-
volatile uint8_t reserved3[0xda];
324+
/* 0x26-0x2f: reserved_26_2f */
325+
volatile uint8_t reserved_26_2f[10];
326+
/* 0x30: PMC4 Status Register */
327+
volatile uint8_t PM4STS;
328+
/* 0x31: PMC4 Data Out Port */
329+
volatile uint8_t PM4DO;
330+
/* 0x32: PMC4 Data In Port */
331+
volatile uint8_t PM4DI;
332+
/* 0x33: PMC4 Control */
333+
volatile uint8_t PM4CTL;
334+
/* 0x34: PMC4 Interrupt Control */
335+
volatile uint8_t PM4IC;
336+
/* 0x35: PMC4 Interrupt Enable*/
337+
volatile uint8_t PM4IE;
338+
/* 0x36-0x3f: reserved_36_3f */
339+
volatile uint8_t reserved_36_3f[10];
340+
/* 0x40: PMC5 Status Register */
341+
volatile uint8_t PM5STS;
342+
/* 0x41: PMC5 Data Out Port */
343+
volatile uint8_t PM5DO;
344+
/* 0x42: PMC5 Data In Port */
345+
volatile uint8_t PM5DI;
346+
/* 0x43: PMC5 Control */
347+
volatile uint8_t PM5CTL;
348+
/* 0x44: PMC5 Interrupt Control */
349+
volatile uint8_t PM5IC;
350+
/* 0x45: PMC5 Interrupt Enable*/
351+
volatile uint8_t PM5IE;
352+
/* 0x46-0xff: reserved_46_ff */
353+
volatile uint8_t reserved_46_ff[0xba];
324354
};
325355

326356
/* Input Buffer Full Interrupt Enable */
@@ -338,8 +368,19 @@ struct pmc_regs {
338368
#define PMC_PM2CTL_IBFIE BIT(0)
339369
/* General Purpose Flag */
340370
#define PMC_PM2STS_GPF BIT(2)
371+
341372
/* PMC3 Input Buffer Full Interrupt Enable */
342-
#define PMC_PM3CTL_IBFIE BIT(0)
373+
#define PMC_PM3CTL_IBFIE BIT(0)
374+
/* A2 Address (A2) */
375+
#define PMC_PM3STS_A2_ADDR BIT(3)
376+
/* Input Buffer Full Interrupt Enable */
377+
#define PMC_PM4CTL_IBFIE BIT(0)
378+
/* A2 Address (A2) */
379+
#define PMC_PM4STS_A2_ADDR BIT(3)
380+
/* Input Buffer Full Interrupt Enable */
381+
#define PMC_PM5CTL_IBFIE BIT(0)
382+
/* A2 Address (A2) */
383+
#define PMC_PM5STS_A2_ADDR BIT(3)
343384

344385
/*
345386
* Dedicated Interrupt
@@ -797,6 +838,54 @@ static const struct ec2i_t pmc3_settings[] = {
797838
};
798839
#endif
799840

841+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2
842+
#define IT8XXX2_ESPI_HOST_IO_PVT2_DATA_PORT_MSB \
843+
((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2_PORT_NUM >> 8) & 0xff)
844+
#define IT8XXX2_ESPI_HOST_IO_PVT2_DATA_PORT_LSB \
845+
(CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2_PORT_NUM & 0xff)
846+
#define IT8XXX2_ESPI_HOST_IO_PVT2_CMD_PORT_MSB \
847+
(((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2_PORT_NUM + 4) >> 8) & 0xff)
848+
#define IT8XXX2_ESPI_HOST_IO_PVT2_CMD_PORT_LSB \
849+
((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2_PORT_NUM + 4) & 0xff)
850+
static const struct ec2i_t pmc4_settings[] = {
851+
/* Select logical device 18h(PMC4) */
852+
{HOST_INDEX_LDN, LDN_PMC4},
853+
/* I/O Port Base Address (data/command ports) */
854+
{HOST_INDEX_IOBAD0_MSB, IT8XXX2_ESPI_HOST_IO_PVT2_DATA_PORT_MSB},
855+
{HOST_INDEX_IOBAD0_LSB, IT8XXX2_ESPI_HOST_IO_PVT2_DATA_PORT_LSB},
856+
{HOST_INDEX_IOBAD1_MSB, IT8XXX2_ESPI_HOST_IO_PVT2_CMD_PORT_MSB},
857+
{HOST_INDEX_IOBAD1_LSB, IT8XXX2_ESPI_HOST_IO_PVT2_CMD_PORT_LSB},
858+
/* Set IRQ=00h for logical device */
859+
{HOST_INDEX_IRQNUMX, 0x00},
860+
/* Enable logical device */
861+
{HOST_INDEX_LDA, 0x01},
862+
};
863+
#endif /* CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2 */
864+
865+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3
866+
#define IT8XXX2_ESPI_HOST_IO_PVT3_DATA_PORT_MSB \
867+
((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3_PORT_NUM >> 8) & 0xff)
868+
#define IT8XXX2_ESPI_HOST_IO_PVT3_DATA_PORT_LSB \
869+
(CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3_PORT_NUM & 0xff)
870+
#define IT8XXX2_ESPI_HOST_IO_PVT3_CMD_PORT_MSB \
871+
(((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3_PORT_NUM + 4) >> 8) & 0xff)
872+
#define IT8XXX2_ESPI_HOST_IO_PVT3_CMD_PORT_LSB \
873+
((CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3_PORT_NUM + 4) & 0xff)
874+
static const struct ec2i_t pmc5_settings[] = {
875+
/* Select logical device 19h(PMC5) */
876+
{HOST_INDEX_LDN, LDN_PMC5},
877+
/* I/O Port Base Address (data/command ports) */
878+
{HOST_INDEX_IOBAD0_MSB, IT8XXX2_ESPI_HOST_IO_PVT3_DATA_PORT_MSB},
879+
{HOST_INDEX_IOBAD0_LSB, IT8XXX2_ESPI_HOST_IO_PVT3_DATA_PORT_LSB},
880+
{HOST_INDEX_IOBAD1_MSB, IT8XXX2_ESPI_HOST_IO_PVT3_CMD_PORT_MSB},
881+
{HOST_INDEX_IOBAD1_LSB, IT8XXX2_ESPI_HOST_IO_PVT3_CMD_PORT_LSB},
882+
/* Set IRQ=00h for logical device */
883+
{HOST_INDEX_IRQNUMX, 0x00},
884+
/* Enable logical device */
885+
{HOST_INDEX_LDA, 0x01},
886+
};
887+
#endif /* CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3 */
888+
800889
#ifdef CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD
801890
#define IT8XXX2_ESPI_HC_DATA_PORT_MSB \
802891
((CONFIG_ESPI_PERIPHERAL_HOST_CMD_DATA_PORT_NUM >> 8) & 0xff)
@@ -1007,6 +1096,12 @@ static void pnpcfg_it8xxx2_init(const struct device *dev)
10071096
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT
10081097
PNPCFG(pmc3);
10091098
#endif
1099+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2
1100+
PNPCFG(pmc4);
1101+
#endif
1102+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3
1103+
PNPCFG(pmc5);
1104+
#endif
10101105
#if defined(CONFIG_ESPI_PERIPHERAL_EC_HOST_CMD) || \
10111106
defined(CONFIG_ESPI_PERIPHERAL_ACPI_SHM_REGION)
10121107
PNPCFG(smfi);
@@ -1252,6 +1347,60 @@ static void pmc3_it8xxx2_init(const struct device *dev)
12521347
}
12531348
#endif
12541349

1350+
/* PMC4 (Host private port 2) */
1351+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2
1352+
static void pmc4_it8xxx2_ibf_isr(const struct device *dev)
1353+
{
1354+
const struct espi_it8xxx2_config *const config = dev->config;
1355+
struct espi_it8xxx2_data *const data = dev->data;
1356+
struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
1357+
struct espi_event evt = {.evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
1358+
.evt_details = ESPI_PERIPHERAL_HOST_IO_PVT2,
1359+
.evt_data = ESPI_PERIPHERAL_NODATA};
1360+
1361+
evt.evt_data = pmc_reg->PM4DI;
1362+
espi_send_callbacks(&data->callbacks, dev, evt);
1363+
}
1364+
1365+
static void pmc4_it8xxx2_init(const struct device *dev)
1366+
{
1367+
const struct espi_it8xxx2_config *const config = dev->config;
1368+
struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
1369+
1370+
/* Enable pmc4 input buffer full interrupt */
1371+
pmc_reg->PM4CTL |= PMC_PM4CTL_IBFIE;
1372+
IRQ_CONNECT(IT8XXX2_PMC4_IBF_IRQ, 0, pmc4_it8xxx2_ibf_isr, DEVICE_DT_INST_GET(0), 0);
1373+
irq_enable(IT8XXX2_PMC4_IBF_IRQ);
1374+
}
1375+
#endif /* CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2 */
1376+
1377+
/* PMC5 (Host private port 3) */
1378+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3
1379+
static void pmc5_it8xxx2_ibf_isr(const struct device *dev)
1380+
{
1381+
const struct espi_it8xxx2_config *const config = dev->config;
1382+
struct espi_it8xxx2_data *const data = dev->data;
1383+
struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
1384+
struct espi_event evt = {.evt_type = ESPI_BUS_PERIPHERAL_NOTIFICATION,
1385+
.evt_details = ESPI_PERIPHERAL_HOST_IO_PVT3,
1386+
.evt_data = ESPI_PERIPHERAL_NODATA};
1387+
1388+
evt.evt_data = pmc_reg->PM5DI;
1389+
espi_send_callbacks(&data->callbacks, dev, evt);
1390+
}
1391+
1392+
static void pmc5_it8xxx2_init(const struct device *dev)
1393+
{
1394+
const struct espi_it8xxx2_config *const config = dev->config;
1395+
struct pmc_regs *const pmc_reg = (struct pmc_regs *)config->base_pmc;
1396+
1397+
/* Enable pmc5 input buffer full interrupt */
1398+
pmc_reg->PM5CTL |= PMC_PM5CTL_IBFIE;
1399+
IRQ_CONNECT(IT8XXX2_PMC5_IBF_IRQ, 0, pmc5_it8xxx2_ibf_isr, DEVICE_DT_INST_GET(0), 0);
1400+
irq_enable(IT8XXX2_PMC5_IBF_IRQ);
1401+
}
1402+
#endif /* CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3 */
1403+
12551404
#define IT8XXX2_ESPI_VW_SEND_TIMEOUT_US (USEC_PER_MSEC * 10)
12561405

12571406
/* eSPI api functions */
@@ -2617,6 +2766,14 @@ static int espi_it8xxx2_init(const struct device *dev)
26172766
/* enable pmc3 for host private port */
26182767
pmc3_it8xxx2_init(dev);
26192768
#endif
2769+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT2
2770+
/* enable pmc4 for host private port */
2771+
pmc4_it8xxx2_init(dev);
2772+
#endif
2773+
#ifdef CONFIG_ESPI_PERIPHERAL_HOST_IO_PVT3
2774+
/* enable pmc5 for host private port */
2775+
pmc5_it8xxx2_init(dev);
2776+
#endif
26202777

26212778
/* Reset vwidx_cached_flag[] at initialization */
26222779
espi_it8xxx2_reset_vwidx_cache(dev);

‎dts/riscv/ite/it51xxx.dtsi

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1247,7 +1247,9 @@
12471247
IT51XXX_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH
12481248
IT51XXX_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH
12491249
IT51XXX_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH
1250-
IT51XXX_IRQ_PMC3_IBF IRQ_TYPE_LEVEL_HIGH>;
1250+
IT51XXX_IRQ_PMC3_IBF IRQ_TYPE_LEVEL_HIGH
1251+
IT51XXX_IRQ_PMC4_IBF IRQ_TYPE_LEVEL_HIGH
1252+
IT51XXX_IRQ_PMC5_IBF IRQ_TYPE_LEVEL_HIGH>;
12511253
interrupt-parent = <&intc>;
12521254
wucctrl = <&wuc_wu42>;
12531255
#address-cells = <1>;

‎dts/riscv/ite/it8xxx2.dtsi

Lines changed: 3 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -442,7 +442,9 @@
442442
IT8XXX2_IRQ_PCH_P80 IRQ_TYPE_LEVEL_HIGH
443443
IT8XXX2_IRQ_PMC2_IBF IRQ_TYPE_LEVEL_HIGH
444444
IT8XXX2_IRQ_WKINTD IRQ_TYPE_LEVEL_HIGH
445-
IT8XXX2_IRQ_PMC3_IBF IRQ_TYPE_LEVEL_HIGH>;
445+
IT8XXX2_IRQ_PMC3_IBF IRQ_TYPE_LEVEL_HIGH
446+
IT8XXX2_IRQ_PMC4_IBF IRQ_TYPE_LEVEL_HIGH
447+
IT8XXX2_IRQ_PMC5_IBF IRQ_TYPE_LEVEL_HIGH>;
446448
interrupt-parent = <&intc>;
447449
wucctrl = <&wuc_wu42>;
448450
#address-cells = <1>;

‎include/zephyr/dt-bindings/interrupt-controller/ite-intc.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -59,6 +59,7 @@
5959
#define IT8XXX2_IRQ_TIMER2 58
6060
/* Group 8 */
6161
#define IT8XXX2_IRQ_PMC3_IBF 67
62+
#define IT8XXX2_IRQ_PMC4_IBF 69
6263
/* Group 9 */
6364
#define IT8XXX2_IRQ_WU70 72
6465
#define IT8XXX2_IRQ_WU71 73
@@ -141,6 +142,7 @@
141142
#define IT8XXX2_IRQ_WU124 145
142143
#define IT8XXX2_IRQ_WU125 146
143144
#define IT8XXX2_IRQ_WU126 147
145+
#define IT8XXX2_IRQ_PMC5_IBF 150
144146
#define IT8XXX2_IRQ_V_CMP 151
145147
/* Group 19 */
146148
#define IT8XXX2_IRQ_SMB_E 152

‎include/zephyr/dt-bindings/interrupt-controller/ite-it51xxx-intc.h

Lines changed: 2 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -61,6 +61,7 @@
6161
#define IT51XXX_IRQ_TIMER2 58
6262
/* Group 8 */
6363
#define IT51XXX_IRQ_PMC3_IBF 67
64+
#define IT51XXX_IRQ_PMC4_IBF 69
6465
/* Group 9 */
6566
#define IT51XXX_IRQ_WU70 72
6667
#define IT51XXX_IRQ_WU71 73
@@ -136,6 +137,7 @@
136137
#define IT51XXX_IRQ_WU142 142
137138
/* Group 18 */
138139
#define IT51XXX_IRQ_WU127 148
140+
#define IT51XXX_IRQ_PMC5_IBF 150
139141
#define IT51XXX_IRQ_V_CMP 151
140142
/* Group 19 */
141143
#define IT51XXX_IRQ_PECI 152

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