soc: stm32: add 802.15.4 support for STM32WBA

Add 802.15.4 support in hci_if files

Signed-off-by: Vincent Tardy <[email protected]>

Author: vtardy-st

soc/st/stm32/stm32wbax/CMakeLists.txt

@@ -10,12 +10,10 @@ zephyr_sources_ifdef(CONFIG_PM
   )
 
 zephyr_sources_ifdef(CONFIG_POWEROFF poweroff.c)
-
-if(CONFIG_BT_STM32WBA)
+if(CONFIG_BT_STM32WBA OR CONFIG_IEEE802154_STM32WBA)
   zephyr_include_directories(hci_if)
-
   zephyr_sources(hci_if/linklayer_plat_adapt.c)
-  zephyr_sources(hci_if/bleplat.c)
+  zephyr_sources(hci_if/sys_wireless_plat.c)
   zephyr_sources(hci_if/host_stack_if.c)
   zephyr_sources(hci_if/ll_sys_if_adapt.c)
   zephyr_sources(hci_if/stm32_timer.c)

soc/st/stm32/stm32wbax/Kconfig.defconfig

@@ -50,6 +50,29 @@ config SYSTEM_WORKQUEUE_STACK_SIZE
 
 endif
 
+config IEEE802154_STM32WBA
+	select DYNAMIC_INTERRUPTS
+	select DYNAMIC_DIRECT_INTERRUPTS
+	select ENTROPY_GENERATOR
+	select HAS_STM32LIB
+
+if IEEE802154_STM32WBA
+
+config FPU
+	default y
+
+choice LIBC_IMPLEMENTATION
+	default NEWLIB_LIBC
+endchoice
+
+config ENTROPY_STM32_CLK_CHECK
+	default n
+
+config SYSTEM_WORKQUEUE_STACK_SIZE
+	default 2048
+
+endif # IEEE802154_STM32WBA
+
 if PM_S2RAM
 
 config COUNTER

soc/st/stm32/stm32wbax/hci_if/host_stack_if.c

@@ -7,28 +7,41 @@
 #include <zephyr/kernel.h>
 #include <zephyr/init.h>
 
+#include "app_conf.h"
+#if defined(CONFIG_BT_STM32WBA)
 #include "blestack.h"
 #include "bpka.h"
+#endif /* CONFIG_BT_STM32WBA */
 #include "ll_intf.h"
 
 K_MUTEX_DEFINE(ble_ctrl_stack_mutex);
-struct k_work_q ble_ctrl_work_q, ll_work_q;
+#if defined(CONFIG_BT_STM32WBA)
+struct k_work_q ble_ctrl_work_q;
 struct k_work ble_ctrl_stack_work, bpka_work;
-
+#endif /* CONFIG_BT_STM32WBA */
+struct k_work_q ll_work_q;
 uint8_t ll_state_busy;
 
 /* TODO: More tests to be done to optimize thread stacks' sizes */
+#if defined(CONFIG_BT_STM32WBA)
 #define BLE_CTRL_THREAD_STACK_SIZE (256 * 7)
-#define LL_THREAD_STACK_SIZE (256 * 7)
 #define BLE_CTRL_THREAD_PRIO (14)
+#endif /* CONFIG_BT_STM32WBA */
+#define LL_THREAD_STACK_SIZE (256 * 7)
+
 /* The LL thread has higher priority than the BLE CTRL thread and the Zephyr BLE stack threads */
 #define LL_THREAD_PRIO (4)
 
+#if defined(CONFIG_BT_STM32WBA)
 K_THREAD_STACK_DEFINE(ble_ctrl_work_area, BLE_CTRL_THREAD_STACK_SIZE);
+#endif /* CONFIG_BT_STM32WBA */
 K_THREAD_STACK_DEFINE(ll_work_area, LL_THREAD_STACK_SIZE);
 
+#if defined(CONFIG_BT_STM32WBA)
 void HostStack_Process(void);
+#endif /* CONFIG_BT_STM32WBA */
 
+#if defined(CONFIG_BT_STM32WBA)
 static void ble_ctrl_stack_handler(struct k_work *work)
 {
 	uint8_t running = 0x00;
@@ -53,25 +66,33 @@ static void bpka_work_handler(struct k_work *work)
 {
 	BPKA_BG_Process();
 }
+#endif /* CONFIG_BT_STM32WBA */
 
-static int stm32wba_ble_ctrl_init(void)
+static int stm32wba_ctrl_init(void)
 {
+	struct k_work_queue_config ll_cfg = {.name = "LL thread"};
+
+#if defined(CONFIG_BT_STM32WBA)
+	struct k_work_queue_config ble_ctrl_cfg = {.name = "ble ctrl thread"};
+
 	k_work_queue_init(&ble_ctrl_work_q);
 	k_work_queue_start(&ble_ctrl_work_q, ble_ctrl_work_area,
 			   K_THREAD_STACK_SIZEOF(ble_ctrl_work_area),
-			   BLE_CTRL_THREAD_PRIO, NULL);
+			   BLE_CTRL_THREAD_PRIO, &ble_ctrl_cfg);
+
+	k_work_init(&ble_ctrl_stack_work, &ble_ctrl_stack_handler);
+	k_work_init(&bpka_work, &bpka_work_handler);
+#endif /* CONFIG_BT_STM32WBA */
 
 	k_work_queue_init(&ll_work_q);
 	k_work_queue_start(&ll_work_q, ll_work_area,
 			   K_THREAD_STACK_SIZEOF(ll_work_area),
-			   LL_THREAD_PRIO, NULL);
-
-	k_work_init(&ble_ctrl_stack_work, &ble_ctrl_stack_handler);
-	k_work_init(&bpka_work, &bpka_work_handler);
+			   LL_THREAD_PRIO, &ll_cfg);
 
 	return 0;
 }
 
+#if defined(CONFIG_BT_STM32WBA)
 void HostStack_Process(void)
 {
 	k_work_submit_to_queue(&ble_ctrl_work_q, &ble_ctrl_stack_work);
@@ -81,5 +102,6 @@ void BPKACB_Process(void)
 {
 	k_work_submit_to_queue(&ble_ctrl_work_q, &bpka_work);
 }
+#endif /* CONFIG_BT_STM32WBA */
 
-SYS_INIT(stm32wba_ble_ctrl_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
+SYS_INIT(stm32wba_ctrl_init, POST_KERNEL, CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);

soc/st/stm32/stm32wbax/hci_if/linklayer_plat_adapt.c

@@ -285,6 +285,16 @@ void LINKLAYER_PLAT_DisableOSContextSwitch(void)
 	 **/
 }
 
+uint32_t LINKLAYER_PLAT_GetSTCompanyID(void)
+{
+	return LL_FLASH_GetSTCompanyID();
+}
+
+uint32_t LINKLAYER_PLAT_GetUDN(void)
+{
+	return LL_FLASH_GetUDN();
+}
+
 void LINKLAYER_PLAT_EnableBackupDomainAccess(void)
 {
 	stm32_backup_domain_enable_access();

soc/st/stm32/stm32wbax/hci_if/ll_sys_if_adapt.c

@@ -15,8 +15,9 @@ LOG_MODULE_REGISTER(ll_sys_if_adapt);
 #if defined(CONFIG_BT_STM32WBA_USE_TEMP_BASED_CALIB)
 #include <zephyr/drivers/sensor.h>
 #endif /* defined(CONFIG_BT_STM32WBA_USE_TEMP_BASED_CALIB) */
-
+#if defined(CONFIG_BT_STM32WBA)
 extern struct k_mutex ble_ctrl_stack_mutex;
+#endif /* CONFIG_BT_STM32WBA */
 extern struct k_work_q ll_work_q;
 struct k_work ll_sys_work;
 
@@ -27,9 +28,13 @@ static struct k_work temp_calibration_work;
 
 static void ll_sys_bg_process_handler(struct k_work *work)
 {
+#if defined(CONFIG_BT_STM32WBA)
 	k_mutex_lock(&ble_ctrl_stack_mutex, K_FOREVER);
 	ll_sys_bg_process();
 	k_mutex_unlock(&ble_ctrl_stack_mutex);
+#else
+	ll_sys_bg_process();
+#endif /* CONFIG_BT_STM32WBA */
 }
 
 void ll_sys_schedule_bg_process(void)

soc/st/stm32/stm32wbax/hci_if/bleplat.c renamed to soc/st/stm32/stm32wbax/hci_if/sys_wireless_plat.c

@@ -11,13 +11,14 @@
 #include <zephyr/drivers/clock_control/stm32_clock_control.h>
 
 #include <stm32_ll_rng.h>
-
+#if defined(CONFIG_BT_STM32WBA)
 #include "bleplat.h"
 #include "bpka.h"
+#endif /* CONFIG_BT_STM32WBA */
 #include "linklayer_plat.h"
 
 #define LOG_LEVEL CONFIG_SOC_LOG_LEVEL
-LOG_MODULE_REGISTER(ble_plat);
+LOG_MODULE_REGISTER(sys_wireless_plat);
 
 RAMCFG_HandleTypeDef hramcfg_SRAM1;
 const struct device *rng_dev = DEVICE_DT_GET(DT_CHOSEN(zephyr_entropy));
@@ -30,6 +31,7 @@ struct entropy_stm32_rng_dev_cfg {
 	struct stm32_pclken *pclken;
 };
 
+#if defined(CONFIG_BT_STM32WBA)
 void BLEPLAT_Init(void)
 {
 	BPKA_Reset();
@@ -70,6 +72,7 @@ void BPKACB_Complete(void)
 {
 	BLEPLATCB_PkaComplete();
 }
+#endif /* CONFIG_BT_STM32WBA */
 
 void MX_RAMCFG_Init(void)
 {