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boards: st: n6: use hse as system source clock
Use HSE as system source clock and adjust the different clock parameters to use the highest admissible frequency (according to datasheet DS14791): - CPU clock: 800MHz - NPU clock: 1000MHz - AXI clock: 800MHz - AHB clock: 200MHz Remove the setting of APB prescalers since they are constants set to 1. Signed-off-by: Guillaume Gautier <[email protected]>
1 parent 9f02634 commit f5a5dfc

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+39
-27
lines changed

2 files changed

+39
-27
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boards/st/nucleo_n657x0_q/nucleo_n657x0_q_common.dtsi

Lines changed: 17 additions & 11 deletions
Original file line numberDiff line numberDiff line change
@@ -68,28 +68,37 @@
6868
};
6969

7070
&pll1 {
71-
clocks = <&clk_hsi>;
72-
div-m = <4>;
73-
mul-n = <75>;
71+
clocks = <&clk_hse>;
72+
div-m = <3>;
73+
mul-n = <150>;
74+
div-p1 = <1>;
75+
div-p2 = <1>;
76+
status = "okay";
77+
};
78+
79+
&pll3 {
80+
clocks = <&clk_hse>;
81+
div-m = <3>;
82+
mul-n = <125>;
7483
div-p1 = <1>;
7584
div-p2 = <1>;
7685
status = "okay";
7786
};
7887

7988
&ic1 {
8089
pll-src = <1>;
81-
ic-div = <2>;
90+
ic-div = <3>;
8291
status = "okay";
8392
};
8493

8594
&ic2 {
8695
pll-src = <1>;
87-
ic-div = <3>;
96+
ic-div = <6>;
8897
status = "okay";
8998
};
9099

91100
&ic6 {
92-
pll-src = <1>;
101+
pll-src = <3>;
93102
ic-div = <2>;
94103
status = "okay";
95104
};
@@ -107,7 +116,7 @@
107116

108117
&cpusw {
109118
clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
110-
clock-frequency = <DT_FREQ_M(600)>;
119+
clock-frequency = <DT_FREQ_M(800)>;
111120
status = "okay";
112121
};
113122

@@ -116,10 +125,7 @@
116125
clocks = <&ic2>;
117126
clock-frequency = <DT_FREQ_M(400)>;
118127
ahb-prescaler = <2>;
119-
apb1-prescaler = <1>;
120-
apb2-prescaler = <1>;
121-
apb4-prescaler = <1>;
122-
apb5-prescaler = <1>;
128+
timg-prescaler = <2>;
123129
};
124130

125131
&adc1 {

boards/st/stm32n6570_dk/stm32n6570_dk_common.dtsi

Lines changed: 22 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -60,20 +60,29 @@
6060
};
6161

6262
&pll1 {
63-
clocks = <&clk_hsi>;
64-
div-m = <4>;
65-
mul-n = <75>;
63+
clocks = <&clk_hse>;
64+
div-m = <3>;
65+
mul-n = <150>;
6666
div-p1 = <1>;
6767
div-p2 = <1>;
6868
status = "okay";
6969
};
7070

7171
&pll2 {
7272
clocks = <&clk_hsi>;
73-
div-m = <4>;
74-
mul-n = <24>;
75-
div-p1 = <2>;
76-
div-p2 = <2>;
73+
div-m = <2>;
74+
mul-n = <48>;
75+
div-p1 = <1>;
76+
div-p2 = <1>;
77+
status = "okay";
78+
};
79+
80+
&pll3 {
81+
clocks = <&clk_hse>;
82+
div-m = <3>;
83+
mul-n = <125>;
84+
div-p1 = <1>;
85+
div-p2 = <1>;
7786
status = "okay";
7887
};
7988

@@ -88,24 +97,24 @@
8897

8998
&ic1 {
9099
pll-src = <1>;
91-
ic-div = <2>;
100+
ic-div = <3>;
92101
status = "okay";
93102
};
94103

95104
&ic2 {
96105
pll-src = <1>;
97-
ic-div = <3>;
106+
ic-div = <6>;
98107
status = "okay";
99108
};
100109

101110
&ic4 {
102111
pll-src = <2>;
103-
ic-div = <2>;
112+
ic-div = <32>;
104113
status = "okay";
105114
};
106115

107116
&ic6 {
108-
pll-src = <1>;
117+
pll-src = <3>;
109118
ic-div = <2>;
110119
status = "okay";
111120
};
@@ -129,7 +138,7 @@
129138

130139
&cpusw {
131140
clocks = <&rcc STM32_SRC_IC1 CPU_SEL(3)>;
132-
clock-frequency = <DT_FREQ_M(600)>;
141+
clock-frequency = <DT_FREQ_M(800)>;
133142
status = "okay";
134143
};
135144

@@ -138,10 +147,7 @@
138147
clocks = <&ic2>;
139148
clock-frequency = <DT_FREQ_M(400)>;
140149
ahb-prescaler = <2>;
141-
apb1-prescaler = <1>;
142-
apb2-prescaler = <1>;
143-
apb4-prescaler = <1>;
144-
apb5-prescaler = <1>;
150+
timg-prescaler = <2>;
145151
};
146152

147153
&adc1 {

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