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1 parent 8df15a2 commit f5d8fe0Copy full SHA for f5d8fe0
doc/releases/release-notes-3.6.rst
@@ -59,6 +59,12 @@ Architectures
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* ARC
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+ * Improvements for ARCv3 processors (HS5x & HS6x): enable hardware prefetcher
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+ and shared cluster cache (SCM - Shared Cluster Memory).
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+ * Disabled Thread-local Storage support for platforms with two or more register banks.
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+ * Fixed unstable work of application built with MetaWare toolchain for hardware
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+ platforms (garbage in .device_states section).
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+
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* ARM
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* MPU regions are now always cleared before initialization.
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