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tests: drivers: pinctrl: gd32: add DT AF parse test
Add a test to check that DT information for AF model is extracted correctly. Signed-off-by: Gerard Marull-Paretas <[email protected]>
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‎tests/drivers/pinctrl/gd32/CMakeLists.txt‎

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# Copyright (c) 2021 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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cmake_minimum_required(VERSION 3.20.0)
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find_package(Zephyr REQUIRED HINTS $ENV{ZEPHYR_BASE})
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project(pinctrl_gd32)
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target_sources(app PRIVATE ../common/test_device.c)
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if(CONFIG_PINCTRL_GD32_AF)
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target_sources(app PRIVATE src/main_af.c)
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endif()

‎tests/drivers/pinctrl/gd32/Kconfig‎

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# Copyright (c) 2021 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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mainmenu "pinctrl GD32 DT Test"
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source "Kconfig.zephyr"
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config PINCTRL_TEST_NON_STATIC
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bool "Enable access to pin control configuration"
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select PINCTRL_NON_STATIC
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help
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This option should be selected by unit tests that need to access the pin
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control configuration defined in a device driver.

‎tests/drivers/pinctrl/gd32/boards/gd32f450i_eval.overlay‎

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/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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* SPDX-License-Identifier: Apache-2.0
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*/
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/ {
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test_device: test_device {
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compatible = "vnd,pinctrl-device";
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pinctrl-0 = <&test_device_default>;
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pinctrl-names = "default";
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};
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};
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&pinctrl {
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test_device_default: test_device_default {
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/* Note: the groups are just meant for testing if properties and
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pins are parsed correctly, but do not necessarily represent a
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feasible combination */
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pins1 {
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pinmux = <GD32_PINMUX_AF('A', 0, AF0)>,
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<GD32_PINMUX_AF('B', 1, AF1)>;
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};
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pins2 {
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pinmux = <GD32_PINMUX_AF('C', 2, AF2)>;
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drive-push-pull;
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};
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pins3 {
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pinmux = <GD32_PINMUX_AF('A', 3, AF3)>;
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drive-open-drain;
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};
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pins4 {
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pinmux = <GD32_PINMUX_AF('B', 4, AF4)>;
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bias-disable;
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};
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pins5 {
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pinmux = <GD32_PINMUX_AF('C', 5, AF5)>;
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bias-pull-up;
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};
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pins6 {
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pinmux = <GD32_PINMUX_AF('A', 6, AF6)>;
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bias-pull-down;
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};
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pins7 {
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pinmux = <GD32_PINMUX_AF('B', 7, AF7)>;
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slew-rate = "max-speed-2mhz";
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};
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pins8 {
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pinmux = <GD32_PINMUX_AF('C', 8, AF8)>;
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slew-rate = "max-speed-25mhz";
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};
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pins9 {
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pinmux = <GD32_PINMUX_AF('A', 9, AF9)>;
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slew-rate = "max-speed-50mhz";
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};
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pins10 {
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pinmux = <GD32_PINMUX_AF('B', 10, AF10)>;
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slew-rate = "max-speed-200mhz";
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};
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pins11 {
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pinmux = <GD32_PINMUX_AF('C', 11, ANALOG)>;
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};
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};
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};

‎tests/drivers/pinctrl/gd32/prj.conf‎

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# Copyright (c) 2021 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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CONFIG_ZTEST=y
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CONFIG_PINCTRL_TEST_NON_STATIC=y

‎tests/drivers/pinctrl/gd32/src/main_af.c‎

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/*
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* Copyright (c) 2021 Teslabs Engineering S.L.
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <drivers/pinctrl.h>
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#include <ztest.h>
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/* pin configuration for test device */
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#define TEST_DEVICE DT_NODELABEL(test_device)
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PINCTRL_DT_DEV_CONFIG_DECLARE(TEST_DEVICE);
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static const struct pinctrl_dev_config *pcfg = PINCTRL_DT_DEV_CONFIG_GET(TEST_DEVICE);
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static void test_dt_extract(void)
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{
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const struct pinctrl_state *scfg;
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pinctrl_soc_pin_t pin;
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zassert_equal(pcfg->state_cnt, 1U, NULL);
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scfg = &pcfg->states[0];
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zassert_equal(scfg->id, PINCTRL_STATE_DEFAULT, NULL);
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zassert_equal(scfg->pin_cnt, 12U, NULL);
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pin = scfg->pins[0];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 0, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF0, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[1];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 1, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF1, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[2];
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zassert_equal(GD32_PORT_GET(pin), 2, NULL);
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zassert_equal(GD32_PIN_GET(pin), 2, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF2, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[3];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 3, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF3, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_OD, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[4];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 4, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF4, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[5];
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zassert_equal(GD32_PORT_GET(pin), 2, NULL);
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zassert_equal(GD32_PIN_GET(pin), 5, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF5, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLUP, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[6];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 6, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF6, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_PULLDOWN, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[7];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 7, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF7, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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pin = scfg->pins[8];
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zassert_equal(GD32_PORT_GET(pin), 2, NULL);
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zassert_equal(GD32_PIN_GET(pin), 8, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF8, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_25MHZ, NULL);
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pin = scfg->pins[9];
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zassert_equal(GD32_PORT_GET(pin), 0, NULL);
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zassert_equal(GD32_PIN_GET(pin), 9, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF9, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_50MHZ, NULL);
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pin = scfg->pins[10];
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zassert_equal(GD32_PORT_GET(pin), 1, NULL);
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zassert_equal(GD32_PIN_GET(pin), 10, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_AF10, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_200MHZ, NULL);
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pin = scfg->pins[11];
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zassert_equal(GD32_PORT_GET(pin), 2, NULL);
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zassert_equal(GD32_PIN_GET(pin), 11, NULL);
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zassert_equal(GD32_AF_GET(pin), GD32_ANALOG, NULL);
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zassert_equal(GD32_PUPD_GET(pin), GD32_PUPD_NONE, NULL);
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zassert_equal(GD32_OTYPE_GET(pin), GD32_OTYPE_PP, NULL);
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zassert_equal(GD32_OSPEED_GET(pin), GD32_OSPEED_2MHZ, NULL);
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}
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void test_main(void)
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{
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ztest_test_suite(pinctrl_gd32,
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ztest_unit_test(test_dt_extract));
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ztest_run_test_suite(pinctrl_gd32);
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}

‎tests/drivers/pinctrl/gd32/testcase.yaml‎

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# Copyright (c) 2021 Teslabs Engineering S.L.
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# SPDX-License-Identifier: Apache-2.0
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tests:
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drivers.pinctrl.gd32_af:
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tags: drivers pinctrl
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platform_allow: gd32f450i_eval

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