dts: arm: GD32F4xx serial SoCs basic device tree description

Introduce GD32F4xx serial SoCs basic device tree description.
Use GD32F405 as the basic device model.

Signed-off-by: HaiLong Yang <[email protected]>

Author: cameled

dts/arm/gigadevice/gd32f405.dtsi

@@ -0,0 +1,125 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <arm/armv7-m.dtsi>
+
+/ {
+	cpus {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		cpu0: cpu@0 {
+			device_type = "cpu";
+			compatible = "arm,cortex-m4f";
+			reg = <0>;
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			mpu: mpu@e000ed90 {
+				compatible = "arm,armv7m-mpu";
+				reg = <0xe000ed90 0x40>;
+				arm,num-mpu-regions = <8>;
+			};
+		};
+	};
+
+	soc {
+		sram0: memory@20000000 {
+			compatible = "mmio-sram";
+		};
+
+		fmc: flash-controller@40023c00 {
+			compatible = "gd,gd32-flash-controller";
+			label = "FLASH_CTRL";
+			reg = <0x40023c00 0x400>;
+			peripheral-id = <6>;
+
+			#address-cells = <1>;
+			#size-cells = <1>;
+
+			flash0: flash@8000000 {
+				compatible = "soc-nv-flash";
+				label = "FLASH_0";
+			};
+		};
+
+		usart0: usart@40011000 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40011000 0x400>;
+			interrupts = <37 0>;
+			rcu-periph-clock = <0x1104>;
+			status = "disabled";
+			label = "usart_0";
+		};
+
+		usart1: usart@40004400 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40004400 0x400>;
+			interrupts = <38 0>;
+			rcu-periph-clock = <0x1011>;
+			status = "disabled";
+			label = "usart_1";
+		};
+
+		usart2: usart@40004800 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40004800 0x400>;
+			interrupts = <39 0>;
+			rcu-periph-clock = <0x1012>;
+			status = "disabled";
+			label = "usart_2";
+		};
+
+		uart3: usart@40004c00 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40004c00 0x400>;
+			interrupts = <52 0>;
+			rcu-periph-clock = <0x1013>;
+			status = "disabled";
+			label = "uart_3";
+		};
+
+		uart4: usart@40005000 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40005000 0x400>;
+			interrupts = <52 0>;
+			rcu-periph-clock = <0x1014>;
+			status = "disabled";
+			label = "uart_4";
+		};
+
+		usart5: usart@40011400 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40011400 0x400>;
+			interrupts = <71 0>;
+			rcu-periph-clock = <0x1105>;
+			status = "disabled";
+			label = "usart_5";
+		};
+
+		uart6: usart@40007800 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40007800 0x400>;
+			interrupts = <82 0>;
+			rcu-periph-clock = <0x101e>;
+			status = "disabled";
+			label = "uart_6";
+		};
+
+		uart7: usart@40007c00 {
+			compatible = "gd,gd32-usart";
+			reg = <0x40007c00 0x400>;
+			interrupts = <83 0>;
+			rcu-periph-clock = <0x101f>;
+			status = "disabled";
+			label = "uart_7";
+		};
+	};
+};
+
+&nvic {
+	arm,num-irq-priority-bits = <4>;
+};

dts/arm/gigadevice/gd32f405vgt6.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32f405.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(1024)>;
+			};
+		};
+
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(192)>;
+		};
+	};
+};

dts/arm/gigadevice/gd32f407.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <gigadevice/gd32f405.dtsi>

dts/arm/gigadevice/gd32f450.dtsi

@@ -0,0 +1,7 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <gigadevice/gd32f405.dtsi>

dts/arm/gigadevice/gd32f450ikh6.dtsi

@@ -0,0 +1,22 @@
+/*
+ * Copyright (c) 2021 BrainCo Inc.
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <mem.h>
+#include <gigadevice/gd32f450.dtsi>
+
+/ {
+	soc {
+		flash-controller@40023c00 {
+			flash0: flash@8000000 {
+				reg = <0x08000000 DT_SIZE_K(3072)>;
+			};
+		};
+
+		sram0: memory@20000000 {
+			reg = <0x20000000 DT_SIZE_K(256)>;
+		};
+	};
+};