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soc: arm: dts: arm: xilinx: Zynq-7000 SoC init code, device tree data
Add SoC-specific code, the basic device tree and Kconfig data as well as the corresponding linker command file for the Xilinx Zynq-7000 family of SoCs. This SoC - either as a QEMU simulation or on actual hardware such as the Avnet/Digilent ZedBoard - is suitable as an ini- tial target for the ARMv7 Cortex-A support. Signed-off-by: Immo Birnbaum <[email protected]>
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‎CODEOWNERS‎

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433433
/dts/riscv/starfive/ @rajnesh-kanwal
434434
/dts/riscv/andes_v5* @cwshu @Teng-Shih-Wei
435435
/dts/arm/armv*m.dtsi @galak @ioannisg
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/dts/arm/armv7-a.dtsi @ibirnbaum
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/dts/arm/armv7-r.dtsi @bbolen @stephanosio
437438
/dts/arm/xilinx/ @bbolen @stephanosio
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/dts/arm/renesas/ @julien-massot

‎dts/arm/armv7-a.dtsi‎

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/*
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* Copyright (c) 2018 Lexmark International, Inc.
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include "skeleton.dtsi"
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/ {
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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ranges;
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};
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};

‎dts/arm/xilinx/zynq7000.dtsi‎

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/*
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* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <mem.h>
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#include <arm/armv7-a.dtsi>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include <dt-bindings/ethernet/xlnx_gem.h>
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/ {
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu@0 {
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device_type = "cpu";
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compatible = "arm,cortex-a9";
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reg = <0>;
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};
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};
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soc {
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interrupt-parent = <&gic>;
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ocm_low: memory@1000 {
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compatible = "xlnx,zynq-ocm";
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reg = <0x00001000 DT_SIZE_K(188)>;
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};
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ocm_high: memory@fffc0000 {
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compatible = "xlnx,zynq-ocm";
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reg = <0xFFFC0000 DT_SIZE_K(256)>;
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};
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arch_timer: timer@f8f00200 {
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compatible = "arm,armv8-timer";
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status = "okay";
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interrupt-names = "irq_0", "irq_1", "irq_2", "irq_3";
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interrupts = <GIC_PPI 13 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 14 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 11 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>,
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<GIC_PPI 10 IRQ_TYPE_EDGE
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IRQ_DEFAULT_PRIORITY>;
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reg = <0xf8f00200 0x1C>;
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label = "arch_timer";
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};
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gic: interrupt-controller@f8f01000 {
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compatible = "arm,gic";
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status = "okay";
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reg = <0xf8f01000 0x1000>,
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<0xf8f00100 0x100>;
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interrupt-controller;
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#interrupt-cells = <4>;
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label = "gic";
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};
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gem0: ethernet@e000b000 {
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compatible = "xlnx,gem";
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status = "disabled";
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reg = <0xe000b000 0x1000>,
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<0xf8000140 0x4>;
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interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 23 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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label = "gem0";
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mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
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phy-poll-interval = <1000>;
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link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
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amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
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amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
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hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
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hw-rx-buffer-offset = <0>;
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hw-tx-buffer-size-full;
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rx-buffer-descriptors = <32>;
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tx-buffer-descriptors = <32>;
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rx-buffer-size = <512>;
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tx-buffer-size = <512>;
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discard-rx-fcs;
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unicast-hash;
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full-duplex;
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};
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gem1: ethernet@e000c000 {
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compatible = "xlnx,gem";
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status = "disabled";
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reg = <0xe000c000 0x1000>,
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<0xf8000144 0x4>;
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interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>,
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<GIC_SPI 46 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0", "irq_1";
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label = "gem1";
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mdio-phy-address = <XLNX_GEM_PHY_AUTO_DETECT>;
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phy-poll-interval = <1000>;
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link-speed = <XLNX_GEM_LINK_SPEED_100MBIT>;
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amba-ahb-dbus-width = <XLNX_GEM_AMBA_AHB_DBUS_WIDTH_32BIT>;
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amba-ahb-burst-length = <XLNX_GEM_AMBA_AHB_BURST_SINGLE>;
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hw-rx-buffer-size = <XLNX_GEM_HW_RX_BUFFER_SIZE_8KB>;
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hw-rx-buffer-offset = <0>;
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hw-tx-buffer-size-full;
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rx-buffer-descriptors = <32>;
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tx-buffer-descriptors = <32>;
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rx-buffer-size = <512>;
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tx-buffer-size = <512>;
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discard-rx-fcs;
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unicast-hash;
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full-duplex;
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};
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uart0: uart@e0000000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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reg = <0xe0000000 0x4c>;
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interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "uart0";
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};
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uart1: uart@e0001000 {
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compatible = "xlnx,xuartps";
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status = "disabled";
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reg = <0xe0001000 0x4c>;
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interrupts = <GIC_SPI 50 IRQ_TYPE_LEVEL
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IRQ_DEFAULT_PRIORITY>;
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interrupt-names = "irq_0";
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label = "uart1";
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};
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};
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};

‎soc/arm/xilinx_zynq7000/CMakeLists.txt‎

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#
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# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_sources(
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soc.c
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)

‎soc/arm/xilinx_zynq7000/Kconfig.defconfig‎

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#
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# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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# SPDX-License-Identifier: Apache-2.0
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#
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if SOC_XILINX_ZYNQ7000 || SOC_XILINX_ZYNQ7000S
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config SOC
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default "xilinx_zynq7000"
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config NUM_IRQS
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int
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# must be >= the highest interrupt number used
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default 96
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# Workaround for not being able to have commas in macro arguments
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DT_CHOSEN_Z_FLASH := zephyr,flash
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config FLASH_SIZE
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default $(dt_chosen_reg_size_int,$(DT_CHOSEN_Z_FLASH),0,K)
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config FLASH_BASE_ADDRESS
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default $(dt_chosen_reg_addr_hex,$(DT_CHOSEN_Z_FLASH))
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endif

‎soc/arm/xilinx_zynq7000/Kconfig.soc‎

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#
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# Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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# SPDX-License-Identifier: Apache-2.0
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#
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config SOC_SERIES_XILINX_ZYNQ7000
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bool "Xilinx Zynq-7000 Core Series"
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select ARM
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select CPU_CORTEX_A9
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select GIC_V1
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select ARM_ARCH_TIMER_ERRATUM_740657 if ARM_ARCH_TIMER
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help
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Enable support for the Xilinx Zynq-7000 SoC series.
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choice
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prompt "Xilinx Zynq-7000 Selection"
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depends on SOC_SERIES_XILINX_ZYNQ7000
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config SOC_XILINX_ZYNQ7000
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bool "Xilinx Zynq-7000 dual-core (XC7Zxxx)"
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config SOC_XILINX_ZYNQ7000S
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bool "Xilinx Zynq-7000 single-core (XC7ZxxxS)"
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endchoice

‎soc/arm/xilinx_zynq7000/linker.ld‎

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/*
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* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <arch/arm/aarch32/cortex_a_r/scripts/linker.ld>

‎soc/arm/xilinx_zynq7000/soc.c‎

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/*
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* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <device.h>
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#include <devicetree.h>
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#include <init.h>
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#include <sys/util.h>
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#include <arch/arm/aarch32/mmu/arm_mmu.h>
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#include "soc.h"
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static const struct arm_mmu_region mmu_regions[] = {
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MMU_REGION_FLAT_ENTRY("vectors",
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0x00000000,
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0x1000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_X),
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MMU_REGION_FLAT_ENTRY("slcr",
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0xF8000000,
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0x1000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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MMU_REGION_FLAT_ENTRY("mpcore",
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0xF8F00000,
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0x2000,
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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MMU_REGION_FLAT_ENTRY("ocm",
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DT_REG_ADDR(DT_CHOSEN(zephyr_ocm)),
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DT_REG_SIZE(DT_CHOSEN(zephyr_ocm)),
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MT_STRONGLY_ORDERED | MPERM_R | MPERM_W),
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/* ARM Arch timer, GIC are covered by the MPCore mapping */
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/* UARTs */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart0), okay)
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MMU_REGION_FLAT_ENTRY("uart0",
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DT_REG_ADDR(DT_NODELABEL(uart0)),
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DT_REG_SIZE(DT_NODELABEL(uart0)),
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MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(uart1), okay)
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MMU_REGION_FLAT_ENTRY("uart1",
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DT_REG_ADDR(DT_NODELABEL(uart1)),
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DT_REG_SIZE(DT_NODELABEL(uart1)),
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MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
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#endif
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/* GEMs */
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gem0), okay)
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MMU_REGION_FLAT_ENTRY("gem0",
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DT_REG_ADDR(DT_NODELABEL(gem0)),
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DT_REG_SIZE(DT_NODELABEL(gem0)),
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MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
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#endif
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#if DT_NODE_HAS_STATUS(DT_NODELABEL(gem1), okay)
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MMU_REGION_FLAT_ENTRY("gem1",
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DT_REG_ADDR(DT_NODELABEL(gem1)),
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DT_REG_SIZE(DT_NODELABEL(gem1)),
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MT_DEVICE | MATTR_SHARED | MPERM_R | MPERM_W),
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#endif
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};
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const struct arm_mmu_config mmu_config = {
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.num_regions = ARRAY_SIZE(mmu_regions),
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.mmu_regions = mmu_regions,
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};
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/**
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* @brief Basic hardware initialization of the Zynq-7000 SoC
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*
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* Performs the basic initialization of the Zynq-7000 SoC.
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*
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* @return 0
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*/
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static int soc_xlnx_zynq7000_init(const struct device *arg)
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{
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ARG_UNUSED(arg);
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NMI_INIT();
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return 0;
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}
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SYS_INIT(soc_xlnx_zynq7000_init, PRE_KERNEL_1,
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CONFIG_KERNEL_INIT_PRIORITY_DEFAULT);
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/* EOF */

‎soc/arm/xilinx_zynq7000/soc.h‎

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/*
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* Copyright (c) 2021 Weidmueller Interface GmbH & Co. KG
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef _SOC__H_
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#define _SOC__H_
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#ifndef _ASMLANGUAGE
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/*
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* The following definitions are required for the inclusion of the CMSIS
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* Common Peripheral Access Layer for aarch32 Cortex-A CPUs:
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*/
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#define __CORTEX_A 9U
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#endif /* !_ASMLANGUAGE */
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#endif /* _SOC__H_ */

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