drivers/clock_control: stm32u5: Fix on flash latency procedure

Instead of computing hclk freq use for flash latency setting after
setting the PLLs, do it right at the beginning of the function.
Indeed, first step of PLL configuration is to switch back sysclock
to HSI source (in case it was initially PLL).
In that case, flash latency is theoretically set in consistency with PLL
driver hclk. So we should "measure" hclk freq at that step rather than
once sysclock is back on HSI.

Signed-off-by: Erwan Gouriou <[email protected]>

Author: erwango

drivers/clock_control/clock_stm32_ll_u5.c

@@ -416,6 +416,9 @@ int stm32_clock_control_init(const struct device *dev)
 
 	ARG_UNUSED(dev);
 
+	/* Current hclk value */
+	old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
+
 	/* Set up indiviual enabled clocks */
 	set_up_fixed_clock_sources();
 
@@ -428,9 +431,6 @@ int stm32_clock_control_init(const struct device *dev)
 	/* Set voltage regulator to comply with targeted system frequency */
 	set_regu_voltage(CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC);
 
-	/* Current hclk value */
-	old_hclk_freq = __LL_RCC_CALC_HCLK_FREQ(get_startup_frequency(), LL_RCC_GetAHBPrescaler());
-
 	/* Set flash latency */
 	/* If freq increases, set flash latency before any clock setting */
 	if (old_hclk_freq < CONFIG_SYS_CLOCK_HW_CYCLES_PER_SEC) {