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gmarullgalak
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drivers: serial: nrfx_uarte: add support for pinctrl
This patch replaces driver specific pin configuration code with the new pinctrl generic API. Notes: - uart driver has not been ported yet (this is an RFC!) - Some build assertions cannot be performed since the driver does not have direct access to pin settings anymore. As a result user will not be notified if HWFC is enabled but RTS/CTS pins are not configured. - Some RX enable checks that were performed using pin information has been replaced with a DT property that informs if RX is enabled or not. Signed-off-by: Gerard Marull-Paretas <[email protected]>
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2 files changed

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-143
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drivers/serial/uart_nrfx_uarte.c

Lines changed: 22 additions & 97 deletions
Original file line numberDiff line numberDiff line change
@@ -9,7 +9,7 @@
99
*/
1010

1111
#include <drivers/uart.h>
12-
#include <hal/nrf_gpio.h>
12+
#include <drivers/pinctrl.h>
1313
#include <hal/nrf_uarte.h>
1414
#include <nrfx_timer.h>
1515
#include <sys/util.h>
@@ -161,12 +161,7 @@ struct uarte_nrfx_data {
161161
struct uarte_nrfx_config {
162162
NRF_UARTE_Type *uarte_regs; /* Instance address */
163163
uint32_t flags;
164-
uint32_t pseltxd; /* PSEL.TXD register value */
165-
uint32_t pselrxd; /* PSEL.RXD register value */
166-
uint32_t pselcts; /* PSEL.CTS register value */
167-
uint32_t pselrts; /* PSEL.RTS register value */
168-
nrf_gpio_pin_pull_t rxd_pull; /* RXD pin pull configuration */
169-
nrf_gpio_pin_pull_t cts_pull; /* CTS pin pull configuration */
164+
bool disable_rx;
170165
#ifdef CONFIG_UART_ASYNC_API
171166
nrfx_timer_t timer;
172167
#endif
@@ -798,9 +793,10 @@ static int uarte_nrfx_rx_enable(const struct device *dev, uint8_t *buf,
798793
int32_t timeout)
799794
{
800795
struct uarte_nrfx_data *data = get_dev_data(dev);
796+
const struct uarte_nrfx_config *cfg = get_dev_config(dev);
801797
NRF_UARTE_Type *uarte = get_uarte_instance(dev);
802798

803-
if (nrf_uarte_rx_pin_get(uarte) == NRF_UARTE_PSEL_DISCONNECTED) {
799+
if (cfg->disable_rx) {
804800
__ASSERT(false, "TX only UARTE instance");
805801
return -ENOTSUP;
806802
}
@@ -1674,26 +1670,11 @@ static int uarte_instance_init(const struct device *dev,
16741670

16751671
data->dev = dev;
16761672

1677-
nrf_gpio_pin_write(cfg->pseltxd, 1);
1678-
nrf_gpio_cfg_output(cfg->pseltxd);
1679-
1680-
if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
1681-
nrf_gpio_cfg_input(cfg->pselrxd, cfg->rxd_pull);
1682-
}
1683-
1684-
nrf_uarte_txrx_pins_set(uarte, cfg->pseltxd, cfg->pselrxd);
1685-
1686-
if (cfg->pselcts != NRF_UARTE_PSEL_DISCONNECTED) {
1687-
nrf_gpio_cfg_input(cfg->pselcts, cfg->cts_pull);
1688-
}
1689-
1690-
if (cfg->pselrts != NRF_UARTE_PSEL_DISCONNECTED) {
1691-
nrf_gpio_pin_write(cfg->pselrts, 1);
1692-
nrf_gpio_cfg_output(cfg->pselrts);
1673+
err = pinctrl_state_set(dev, PINCTRL_STATE_ID_DEFAULT);
1674+
if (err < 0) {
1675+
return err;
16931676
}
16941677

1695-
nrf_uarte_hwfc_pins_set(uarte, cfg->pselrts, cfg->pselcts);
1696-
16971678
err = uarte_nrfx_configure(dev, &get_dev_data(dev)->uart_config);
16981679
if (err) {
16991680
return err;
@@ -1720,7 +1701,7 @@ static int uarte_instance_init(const struct device *dev,
17201701
/* Enable receiver and transmitter */
17211702
nrf_uarte_enable(uarte);
17221703

1723-
if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
1704+
if (!cfg->disable_rx) {
17241705
nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
17251706

17261707
nrf_uarte_rx_buffer_set(uarte, &data->rx_data, 1);
@@ -1750,46 +1731,6 @@ static int uarte_instance_init(const struct device *dev,
17501731
}
17511732

17521733
#ifdef CONFIG_PM_DEVICE
1753-
1754-
static void uarte_nrfx_pins_enable(const struct device *dev, bool enable)
1755-
{
1756-
const struct uarte_nrfx_config *cfg = get_dev_config(dev);
1757-
1758-
if (!(cfg->flags & UARTE_CFG_FLAG_GPIO_MGMT)) {
1759-
return;
1760-
}
1761-
1762-
if (enable) {
1763-
nrf_gpio_pin_write(cfg->pseltxd, 1);
1764-
nrf_gpio_cfg_output(cfg->pseltxd);
1765-
if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
1766-
nrf_gpio_cfg_input(cfg->pselrxd, cfg->rxd_pull);
1767-
}
1768-
1769-
if (IS_RTS_PIN_SET(cfg->flags)) {
1770-
nrf_gpio_pin_write(cfg->pselrts, 1);
1771-
nrf_gpio_cfg_output(cfg->pselrts);
1772-
}
1773-
1774-
if (IS_CTS_PIN_SET(cfg->flags)) {
1775-
nrf_gpio_cfg_input(cfg->pselcts, cfg->cts_pull);
1776-
}
1777-
} else {
1778-
nrf_gpio_cfg_default(cfg->pseltxd);
1779-
if (cfg->pselrxd != NRF_UARTE_PSEL_DISCONNECTED) {
1780-
nrf_gpio_cfg_default(cfg->pselrxd);
1781-
}
1782-
1783-
if (IS_RTS_PIN_SET(cfg->flags)) {
1784-
nrf_gpio_cfg_default(cfg->pselrts);
1785-
}
1786-
1787-
if (IS_CTS_PIN_SET(cfg->flags)) {
1788-
nrf_gpio_cfg_default(cfg->pselcts);
1789-
}
1790-
}
1791-
}
1792-
17931734
/** @brief Pend until TX is stopped.
17941735
*
17951736
* There are 2 configurations that must be handled:
@@ -1832,10 +1773,16 @@ static int uarte_nrfx_pm_control(const struct device *dev,
18321773
#if defined(CONFIG_UART_ASYNC_API) || defined(UARTE_INTERRUPT_DRIVEN)
18331774
struct uarte_nrfx_data *data = get_dev_data(dev);
18341775
#endif
1776+
const struct uarte_nrfx_config *cfg = get_dev_config(dev);
1777+
int ret;
18351778

18361779
switch (action) {
18371780
case PM_DEVICE_ACTION_RESUME:
1838-
uarte_nrfx_pins_enable(dev, true);
1781+
ret = pinctrl_state_set(dev, PINCTRL_STATE_ID_DEFAULT);
1782+
if (ret < 0) {
1783+
return ret;
1784+
}
1785+
18391786
nrf_uarte_enable(uarte);
18401787

18411788
#ifdef CONFIG_UART_ASYNC_API
@@ -1846,7 +1793,7 @@ static int uarte_nrfx_pm_control(const struct device *dev,
18461793
return 0;
18471794
}
18481795
#endif
1849-
if (nrf_uarte_rx_pin_get(uarte) != NRF_UARTE_PSEL_DISCONNECTED) {
1796+
if (!cfg->disable_rx) {
18501797

18511798
nrf_uarte_event_clear(uarte, NRF_UARTE_EVENT_ENDRX);
18521799
nrf_uarte_task_trigger(uarte, NRF_UARTE_TASK_STARTRX);
@@ -1899,7 +1846,11 @@ static int uarte_nrfx_pm_control(const struct device *dev,
18991846

19001847
wait_for_tx_stopped(dev);
19011848
uart_disable(dev);
1902-
uarte_nrfx_pins_enable(dev, false);
1849+
1850+
ret = pinctrl_state_set(dev, PINCTRL_STATE_ID_SLEEP);
1851+
if (ret < 0) {
1852+
return ret;
1853+
}
19031854
break;
19041855
default:
19051856
return -ENOTSUP;
@@ -1913,33 +1864,13 @@ static int uarte_nrfx_pm_control(const struct device *dev,
19131864
#define UARTE_HAS_PROP(idx, prop) DT_NODE_HAS_PROP(UARTE(idx), prop)
19141865
#define UARTE_PROP(idx, prop) DT_PROP(UARTE(idx), prop)
19151866

1916-
#define UARTE_PSEL(idx, pin_prop) \
1917-
COND_CODE_1(UARTE_HAS_PROP(idx, pin_prop), \
1918-
(UARTE_PROP(idx, pin_prop)), \
1919-
(NRF_UARTE_PSEL_DISCONNECTED))
1920-
1921-
#define UARTE_PULL(idx, pull_up_prop) \
1922-
COND_CODE_1(UARTE_PROP(idx, pull_up_prop), \
1923-
(NRF_GPIO_PIN_PULLUP), \
1924-
(NRF_GPIO_PIN_NOPULL))
1925-
1926-
#define HWFC_AVAILABLE(idx) \
1927-
(UARTE_HAS_PROP(idx, rts_pin) || UARTE_HAS_PROP(idx, cts_pin))
1928-
19291867
#define UARTE_IRQ_CONFIGURE(idx, isr_handler) \
19301868
do { \
19311869
IRQ_CONNECT(DT_IRQN(UARTE(idx)), DT_IRQ(UARTE(idx), priority), \
19321870
isr_handler, DEVICE_DT_GET(UARTE(idx)), 0); \
19331871
irq_enable(DT_IRQN(UARTE(idx))); \
19341872
} while (0)
19351873

1936-
#define HWFC_CONFIG_CHECK(idx) \
1937-
BUILD_ASSERT( \
1938-
(UARTE_PROP(idx, hw_flow_control) && HWFC_AVAILABLE(idx)) \
1939-
|| \
1940-
!UARTE_PROP(idx, hw_flow_control) \
1941-
)
1942-
19431874
/* Low power mode is used when rx pin is not defined or in async mode if
19441875
* kconfig option is enabled.
19451876
*/
@@ -1950,7 +1881,6 @@ static int uarte_nrfx_pm_control(const struct device *dev,
19501881
(1))) ? 0 : UARTE_CFG_FLAG_LOW_POWER)
19511882

19521883
#define UART_NRF_UARTE_DEVICE(idx) \
1953-
HWFC_CONFIG_CHECK(idx); \
19541884
UARTE_INT_DRIVEN(idx); \
19551885
UARTE_ASYNC(idx); \
19561886
static struct uarte_nrfx_data uarte_##idx##_data = { \
@@ -1972,12 +1902,7 @@ static int uarte_nrfx_pm_control(const struct device *dev,
19721902
(IS_ENABLED(CONFIG_UART_##idx##_ENHANCED_POLL_OUT) ? \
19731903
UARTE_CFG_FLAG_PPI_ENDTX : 0) | \
19741904
USE_LOW_POWER(idx), \
1975-
.pseltxd = UARTE_PROP(idx, tx_pin), /* must be set */ \
1976-
.pselrxd = UARTE_PSEL(idx, rx_pin), /* optional */ \
1977-
.pselcts = UARTE_PSEL(idx, cts_pin), /* optional */ \
1978-
.pselrts = UARTE_PSEL(idx, rts_pin), /* optional */ \
1979-
.rxd_pull = UARTE_PULL(idx, rx_pull_up), \
1980-
.cts_pull = UARTE_PULL(idx, cts_pull_up), \
1905+
.disable_rx = DT_PROP_OR(UARTE(idx), disable_rx, false), \
19811906
IF_ENABLED(CONFIG_UART_##idx##_NRF_HW_ASYNC, \
19821907
(.timer = NRFX_TIMER_INSTANCE( \
19831908
CONFIG_UART_##idx##_NRF_HW_ASYNC_TIMER),)) \
Lines changed: 4 additions & 46 deletions
Original file line numberDiff line numberDiff line change
@@ -1,4 +1,4 @@
1-
include: uart-controller.yaml
1+
include: [uart-controller.yaml, pinctrl-device.yaml]
22

33
properties:
44
reg:
@@ -7,42 +7,10 @@ properties:
77
interrupts:
88
required: true
99

10-
tx-pin:
11-
type: int
12-
required: true
13-
description: |
14-
The TX pin to use.
15-
16-
For pins P0.0 through P0.31, use the pin number. For example,
17-
to use P0.16 for TX, set:
18-
19-
tx-pin = <16>;
20-
21-
For pins P1.0 through P1.31, add 32 to the pin number. For
22-
example, to use P1.2 for TX, set:
23-
24-
tx-pin = <34>; /* 32 + 2 */
25-
26-
rx-pin:
27-
type: int
28-
required: false
29-
description: |
30-
The RX pin to use. The pin numbering scheme is the same as the
31-
tx-pin property's.
32-
33-
rts-pin:
34-
type: int
35-
required: false
36-
description: |
37-
The RTS pin to use. The pin numbering scheme is the same as the
38-
tx-pin property's.
39-
40-
cts-pin:
41-
type: int
42-
required: false
10+
disable-rx:
11+
type: boolean
4312
description: |
44-
The CTS pin to use. The pin numbering scheme is the same as the
45-
tx-pin property's.
13+
Disable UART reception capabilities.
4614
4715
current-speed:
4816
description: |
@@ -67,13 +35,3 @@ properties:
6735
- 460800
6836
- 921600
6937
- 1000000
70-
71-
rx-pull-up:
72-
type: boolean
73-
required: false
74-
description: Enable pull-up resistor on the RX pin.
75-
76-
cts-pull-up:
77-
type: boolean
78-
required: false
79-
description: Enable pull-up resistor on the CTS pin.

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