Skip to content

Commit f745493

Browse files
Ayush1325fabiobaltieri
Ayush1325
authored and
fabiobaltieri
committed
boards: beagle: pocketbeagle_2: a53: Add GPIO pinmux
- Add pinmux for all header pins that support GPIO functionality. - Ball name is included in case one header supports the same functionality on multiple balls. Signed-off-by: Ayush Singh <[email protected]>
1 parent afff286 commit f745493

File tree

1 file changed

+310
-0
lines changed

1 file changed

+310
-0
lines changed

‎boards/beagle/pocketbeagle_2/pocketbeagle_2_am62_a53-pinctrl.dtsi‎

Lines changed: 310 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -36,4 +36,314 @@
3636
/* (E25) OSPI0_D0.GPIO0_3 */
3737
K3_PINMUX(0x000c, PIN_OUTPUT, MUX_MODE_7)>;
3838
};
39+
40+
P1_02_E18_gpio: P1-02-E18-gpio-pins {
41+
/* (E18) MCASP0_AXR0.GPIO1_10 */
42+
pinmux = <K3_PINMUX(0x01A0, PIN_INPUT, MUX_MODE_7)>;
43+
};
44+
45+
P1_02_AA19_gpio: P1-02-AA19-gpio-pins {
46+
/* (AA19) RGMII2_TX_CTL.GPIO0_87 */
47+
pinmux = <K3_PINMUX(0x0164, PIN_INPUT, MUX_MODE_7)>;
48+
};
49+
50+
P1_04_D20_gpio: P1-04-D20-gpio-pins {
51+
/* (D20) MCASP0_AFSX.GPIO1_12 */
52+
pinmux = <K3_PINMUX(0x01A8, PIN_INPUT, MUX_MODE_7)>;
53+
};
54+
55+
P1_04_Y18_gpio: P1-04-Y18-gpio-pins {
56+
/* (Y18) RGMII2_TD0.GPIO0_89 */
57+
pinmux = <K3_PINMUX(0x016C, PIN_INPUT, MUX_MODE_7)>;
58+
};
59+
60+
P1_06_E19_gpio: P1-06-E19-gpio-pins {
61+
/* (E19) MCASP0_AFSR.GPIO1_13 */
62+
pinmux = <K3_PINMUX(0x01AC, PIN_INPUT, MUX_MODE_7)>;
63+
};
64+
65+
P1_06_AD18_gpio: P1-06-AD18-gpio-pins {
66+
/* (AD18) RGMII1_TD3.GPIO0_78 */
67+
pinmux = <K3_PINMUX(0x0140, PIN_INPUT, MUX_MODE_7)>;
68+
};
69+
70+
P1_08_gpio: P1-08-gpio-pins {
71+
/* (A20) MCASP0_ACLKR.GPIO1_14 */
72+
pinmux = <K3_PINMUX(0x01B0, PIN_INPUT, MUX_MODE_7)>;
73+
};
74+
75+
P1_10_A18_gpio: P1-10-A18-gpio-pins {
76+
/* (A18) EXT_REFCLK1.GPIO1_30 */
77+
pinmux = <K3_PINMUX(0x01F0, PIN_INPUT, MUX_MODE_7)>;
78+
};
79+
80+
P1_10_B19_gpio: P1-10-B19-gpio-pins {
81+
/* (B19) MCASP0_AXR3.GPIO1_7 */
82+
pinmux = <K3_PINMUX(0x0194, PIN_INPUT, MUX_MODE_7)>;
83+
};
84+
85+
P1_12_A19_gpio: P1-12-A19-gpio-pins {
86+
/* (A19) MCASP0_AXR2.GPIO1_8 */
87+
pinmux = <K3_PINMUX(0x0198, PIN_INPUT, MUX_MODE_7)>;
88+
};
89+
90+
P1_12_AE18_gpio: P1-12-AE18-gpio-pins {
91+
/* (AE18) RGMII1_TD2.GPIO0_77 */
92+
pinmux = <K3_PINMUX(0x013C, PIN_INPUT, MUX_MODE_7)>;
93+
};
94+
95+
P1_19_gpio: P1-19-gpio-pins {
96+
/* (AD22) RGMII2_RX_CTL.GPIO1_1 */
97+
pinmux = <K3_PINMUX(0x017C, PIN_INPUT, MUX_MODE_7)>;
98+
};
99+
100+
P1_20_gpio: P1-20-gpio-pins {
101+
/* (Y24) VOUT0_DATA5.GPIO0_50 */
102+
pinmux = <K3_PINMUX(0x00CC, PIN_INPUT, MUX_MODE_7)>;
103+
};
104+
105+
P1_21_gpio: P1-21-gpio-pins {
106+
/* (AE22) RGMII2_RD3.GPIO1_6 */
107+
pinmux = <K3_PINMUX(0x0190, PIN_INPUT, MUX_MODE_7)>;
108+
};
109+
110+
P1_23_gpio: P1-23-gpio-pins {
111+
/* (AC21) RGMII2_RD2.GPIO1_5 */
112+
pinmux = <K3_PINMUX(0x018C, PIN_INPUT, MUX_MODE_7)>;
113+
};
114+
115+
P1_25_gpio: P1-25-gpio-pins {
116+
/* (AB20) RGMII2_RD1.GPIO1_4 */
117+
pinmux = <K3_PINMUX(0x0188, PIN_INPUT, MUX_MODE_7)>;
118+
};
119+
120+
P1_26_K24_gpio: P1-26-K24-gpio-pins {
121+
/* (K24) GPMC0_CSn3.GPIO0_44 */
122+
pinmux = <K3_PINMUX(0x00B4, PIN_INPUT, MUX_MODE_7)>;
123+
};
124+
125+
P1_27_gpio: P1-27-gpio-pins {
126+
/* (AE23) RGMII2_RD0.GPIO1_3 */
127+
pinmux = <K3_PINMUX(0x0184, PIN_INPUT, MUX_MODE_7)>;
128+
};
129+
130+
P1_28_K22_gpio: P1-28-K22-gpio-pins {
131+
/* (K22) GPMC0_CSn2.GPIO0_43 */
132+
pinmux = <K3_PINMUX(0x00B0, PIN_INPUT, MUX_MODE_7)>;
133+
};
134+
135+
P1_29_gpio: P1-29-gpio-pins {
136+
/* (Y20) VOUT0_DE.GPIO0_62 */
137+
pinmux = <K3_PINMUX(0x00FC, PIN_INPUT, MUX_MODE_7)>;
138+
};
139+
140+
P1_30_gpio: P1-30-gpio-pins {
141+
/* (E14) UART0_TXD.GPIO1_21 */
142+
pinmux = <K3_PINMUX(0x01CC, PIN_INPUT, MUX_MODE_7)>;
143+
};
144+
145+
P1_31_gpio: P1-31-gpio-pins {
146+
/* (Y22) VOUT0_DATA14.GPIO0_59 */
147+
pinmux = <K3_PINMUX(0x00F0, PIN_INPUT, MUX_MODE_7)>;
148+
};
149+
150+
P1_32_gpio: P1-32-gpio-pins {
151+
/* (D14) UART0_RXD.GPIO1_20 */
152+
pinmux = <K3_PINMUX(0x01C8, PIN_INPUT, MUX_MODE_7)>;
153+
};
154+
155+
P1_33_A17_gpio: P1-33-A17-gpio-pins {
156+
/* (A17) I2C1_SDA.GPIO1_29 */
157+
pinmux = <K3_PINMUX(0x01EC, PIN_INPUT, MUX_MODE_7)>;
158+
};
159+
160+
P1_33_A17_pwm: P1-33-A15-pwm-pins {
161+
/* (A17) I2C1_SDA.EHRPWM2_B */
162+
pinmux = <K3_PINMUX(0x01EC, PIN_INPUT, MUX_MODE_8)>;
163+
};
164+
165+
P1_33_AA23_gpio: P1-33-AA23-gpio-pins {
166+
/* (AA23) VOUT0_DATA11.GPIO0_56 */
167+
pinmux = <K3_PINMUX(0x00E4, PIN_INPUT, MUX_MODE_7)>;
168+
};
169+
170+
P1_34_gpio: P1-34-gpio-pins {
171+
/* (AD23) RGMII2_RXC.GPIO1_2 */
172+
pinmux = <K3_PINMUX(0x0180, PIN_INPUT, MUX_MODE_7)>;
173+
};
174+
175+
P1_35_gpio: P1-35-gpio-pins {
176+
/* (AE21) RGMII2_TXC.GPIO0_88 */
177+
pinmux = <K3_PINMUX(0x0168, PIN_INPUT, MUX_MODE_7)>;
178+
};
179+
180+
P1_36_V20_gpio: P1-36-V20-gpio-pins {
181+
/* (V20) VOUT0_DATA10.GPIO0_55 */
182+
pinmux = <K3_PINMUX(0x00E0, PIN_INPUT, MUX_MODE_7)>;
183+
};
184+
185+
P1_36_B17_gpio: P1-36-B17-gpio-pins {
186+
/* (B17) I2C1_SCL.GPIO1_28 */
187+
pinmux = <K3_PINMUX(0x01E8, PIN_INPUT, MUX_MODE_7)>;
188+
};
189+
190+
P2_01_AD24_gpio: P2-01-AD24-gpio-pins {
191+
/* (AD24) MDIO0_MDC.GPIO0_86 */
192+
pinmux = <K3_PINMUX(0x0160, PIN_INPUT, MUX_MODE_7)>;
193+
};
194+
195+
P2_01_B20_gpio: P2-01-B20-gpio-pins {
196+
/* (B20) MCASP0_ACLKX.GPIO1_11 */
197+
pinmux = <K3_PINMUX(0x01A4, PIN_INPUT, MUX_MODE_7)>;
198+
};
199+
200+
P2_02_gpio: P2-02-gpio-pins {
201+
/* (U22) VOUT0_DATA0.GPIO0_45 */
202+
pinmux = <K3_PINMUX(0x00B8, PIN_INPUT, MUX_MODE_7)>;
203+
};
204+
205+
P2_03_AB22_gpio: P2-03-AB22-gpio-pins {
206+
/* (AB22) MDIO0_MDIO.GPIO0_85 */
207+
pinmux = <K3_PINMUX(0x015C, PIN_INPUT, MUX_MODE_7)>;
208+
};
209+
210+
P2_03_B18_gpio: P2-03-B18-gpio-pins {
211+
/* (B18) MCASP0_AXR1.GPIO1_9 */
212+
pinmux = <K3_PINMUX(0x019C, PIN_INPUT, MUX_MODE_7)>;
213+
};
214+
215+
P2_04_gpio: P2-04-gpio-pins {
216+
/* (V24) VOUT0_DATA1.GPIO0_46 */
217+
pinmux = <K3_PINMUX(0x00BC, PIN_INPUT, MUX_MODE_7)>;
218+
};
219+
220+
P2_05_C15_gpio: P2-05-C15-gpio-pins {
221+
/* (C15) MCAN0_TX.GPIO1_24 */
222+
pinmux = <K3_PINMUX(0x01D8, PIN_INPUT, MUX_MODE_7)>;
223+
};
224+
225+
P2_06_gpio: P2-06-gpio-pins {
226+
/* (W25) VOUT0_DATA2.GPIO0_47 */
227+
pinmux = <K3_PINMUX(0x00C0, PIN_INPUT, MUX_MODE_7)>;
228+
};
229+
230+
P2_07_E15_gpio: P2-07-E15-gpio-pins {
231+
/* (E15) MCAN0_RX.GPIO1_25 */
232+
pinmux = <K3_PINMUX(0x01DC, PIN_INPUT, MUX_MODE_7)>;
233+
};
234+
235+
P2_08_gpio: P2-08-gpio-pins {
236+
/* (W24) VOUT0_DATA3.GPIO0_48 */
237+
pinmux = <K3_PINMUX(0x00C4, PIN_INPUT, MUX_MODE_7)>;
238+
};
239+
240+
P2_09_A15_gpio: P2-09-A15-gpio-pins {
241+
/* (A15) UART0_CTSn.GPIO1_22 */
242+
pinmux = <K3_PINMUX(0x01D0, PIN_INPUT, MUX_MODE_7)>;
243+
};
244+
245+
P2_10_gpio: P2-10-gpio-pins {
246+
/* (AD21) RGMII2_TD2.GPIO0_91 */
247+
pinmux = <K3_PINMUX(0x0174, PIN_INPUT, MUX_MODE_7)>;
248+
};
249+
250+
P2_11_B15_gpio: P2-11-B15-gpio-pins {
251+
/* (B15) UART0_RTSn.GPIO1_23 */
252+
pinmux = <K3_PINMUX(0x01D4, PIN_INPUT, MUX_MODE_7)>;
253+
};
254+
255+
P2_17_gpio: P2-17-gpio-pins {
256+
/* (AC24) VOUT0_PCLK.GPIO0_64 */
257+
pinmux = <K3_PINMUX(0x0104, PIN_INPUT, MUX_MODE_7)>;
258+
};
259+
260+
P2_18_gpio: P2-18-gpio-pins {
261+
/* (V21) VOUT0_DATA8.GPIO0_53 */
262+
pinmux = <K3_PINMUX(0x00D8, PIN_INPUT, MUX_MODE_7)>;
263+
};
264+
265+
P2_19_gpio: P2-19-gpio-pins {
266+
/* (AC20) RGMII2_TD3.GPIO1_0 */
267+
pinmux = <K3_PINMUX(0x0178, PIN_INPUT, MUX_MODE_7)>;
268+
};
269+
270+
P2_20_gpio: P2-20-gpio-pins {
271+
/* (Y25) VOUT0_DATA4.GPIO0_49 */
272+
pinmux = <K3_PINMUX(0x00C8, PIN_INPUT, MUX_MODE_7)>;
273+
};
274+
275+
P2_22_gpio: P2-22-gpio-pins {
276+
/* (AC25) VOUT0_VSYNC.GPIO0_63 */
277+
pinmux = <K3_PINMUX(0x0100, PIN_INPUT, MUX_MODE_7)>;
278+
};
279+
280+
P2_24_gpio: P2-24-gpio-pins {
281+
/* (Y23) VOUT0_DATA6.GPIO0_51 */
282+
pinmux = <K3_PINMUX(0x00D0, PIN_INPUT, MUX_MODE_7)>;
283+
};
284+
285+
P2_25_gpio: P2-25-gpio-pins {
286+
/* (B14) SPI0_D1.GPIO1_19 */
287+
pinmux = <K3_PINMUX(0x01C4, PIN_INPUT, MUX_MODE_7)>;
288+
};
289+
290+
P2_27_gpio: P2-27-gpio-pins {
291+
/* (B13) SPI0_D0.GPIO1_18 */
292+
pinmux = <K3_PINMUX(0x01C0, PIN_INPUT, MUX_MODE_7)>;
293+
};
294+
295+
P2_28_gpio: P2-28-gpio-pins {
296+
/* (AB24) VOUT0_HSYNC.GPIO0_61 */
297+
pinmux = <K3_PINMUX(0x00F8, PIN_INPUT, MUX_MODE_7)>;
298+
};
299+
300+
P2_29_A14_gpio: P2-29-A14-gpio-pins {
301+
/* (A14) SPI0_CLK.GPIO1_17 */
302+
pinmux = <K3_PINMUX(0x01BC, PIN_INPUT, MUX_MODE_7)>;
303+
};
304+
305+
P2_29_M22_gpio: P2-29-M22-gpio-pins {
306+
/* (M22) GPMC0_DIR.GPIO0_40 */
307+
pinmux = <K3_PINMUX(0x00A4, PIN_INPUT, MUX_MODE_7)>;
308+
};
309+
310+
P2_30_gpio: P2-30-gpio-pins {
311+
/* (AA24) VOUT0_DATA13.GPIO0_58 */
312+
pinmux = <K3_PINMUX(0x00EC, PIN_INPUT, MUX_MODE_7)>;
313+
};
314+
315+
P2_31_A13_gpio: P2-31-A13-gpio-pins {
316+
/* (A13) SPI0_CS0.GPIO1_15 */
317+
pinmux = <K3_PINMUX(0x01B4, PIN_INPUT, MUX_MODE_7)>;
318+
};
319+
320+
P2_31_AA18_gpio: P2-31-AA18-gpio-pins {
321+
/* (AA18) RGMII2_TD1.GPIO0_90 */
322+
pinmux = <K3_PINMUX(0x0170, PIN_INPUT, MUX_MODE_7)>;
323+
};
324+
325+
P2_32_gpio: P2-32-gpio-pins {
326+
/* (AB25) VOUT0_DATA12.GPIO0_57 */
327+
pinmux = <K3_PINMUX(0x00E8, PIN_INPUT, MUX_MODE_7)>;
328+
};
329+
330+
P2_33_gpio: P2-33-gpio-pins {
331+
/* (AA25) VOUT0_DATA7.GPIO0_52 */
332+
pinmux = <K3_PINMUX(0x00D4, PIN_INPUT, MUX_MODE_7)>;
333+
};
334+
335+
P2_34_gpio: P2-34-gpio-pins {
336+
/* (AA21) VOUT0_DATA15.GPIO0_60 */
337+
pinmux = <K3_PINMUX(0x00F4, PIN_INPUT, MUX_MODE_7)>;
338+
};
339+
340+
P2_35_gpio: P2-35-gpio-pins {
341+
/* (W21) VOUT0_DATA9.GPIO0_54 */
342+
pinmux = <K3_PINMUX(0x00DC, PIN_INPUT, MUX_MODE_7)>;
343+
};
344+
345+
P2_36_gpio: P2-36-gpio-pins {
346+
/* (C13) SPI0_CS1.GPIO1_16 */
347+
pinmux = <K3_PINMUX(0x01B8, PIN_INPUT, MUX_MODE_7)>;
348+
};
39349
};

0 commit comments

Comments
 (0)