arch/riscv: Explicitly set MSTATUS.MPRV/MPP before PMP configuration

This commit ensures the mstatus Control and Status Register (CSR) is
in a defined state before proceeding with the Physical Memory Protection
(PMP) setup. This is critical in multi-stage boot environments where a
prior stage may have left mstatus in an indeterminate configuration.

Specifically, at the start of `z_riscv_pmp_init`:

1.  `csr_clear(mstatus, MSTATUS_MPRV)`: Clears the MPRV (Modify
    Privilege) bit. When `MPRV` is 0, load and store memory accesses
    executed in Machine Mode (M-mode) use the actual privilege of
    M-mode. This prevents the PMP configuration code's own memory
    operations from being unintentionally restricted by a lingering
    `MPP` value, as if they were originating from a lower privilege
    level.

2.  `csr_set(mstatus, MSTATUS_MPP)`: Sets the MPP (Machine Previous
    Privilege) field to Machine Mode (binary 11). While clearing
    `MPRV` addresses the immediate memory access concern for the
    init code, setting `MPP` to M-mode establishes a predictable
    default for the prior privilege level.

This explicit state management guarantees that the PMP initialization,
which must run in M-mode, is executed reliably and consistently,
regardless of the `mstatus` state inherited from previous boot stages.

Signed-off-by: Firas Sammoura <[email protected]>

Author: fsammoura1980

arch/riscv/core/pmp.c

@@ -350,6 +350,15 @@ static unsigned int global_pmp_end_index;
  */
 void z_riscv_pmp_init(void)
 {
+	/*
+	 * Ensure we are in M-mode and that memory accesses use M-mode privileges
+	 * (MPRV=0) before configuring PMP registers. This prevents memory accesses
+	 * during PMP setup from being restricted by a lingering MPP state.
+	 * We also set MPP to M-mode to establish a predictable prior privilege level.
+	 */
+	csr_clear(mstatus, MSTATUS_MPRV);
+	csr_set(mstatus, MSTATUS_MPP);
+
 	unsigned long pmp_addr[CONFIG_PMP_SLOTS];
 	unsigned long pmp_cfg[CONFIG_PMP_SLOTS / PMPCFG_STRIDE];
 	unsigned int index = 0;