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iuliana-prodaniuliana-prodan
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soc: nxp: imxrt700: Add i.MXRT700 HiFi1 DSP support
The i.MX RT700 has an ultra-low power Sense Subsystem which includes an ARM Cortex-M33 and Cadence Tensilica HiFi 1 DSP. Here, we add support for the HiFi1 core. Signed-off-by: Iuliana Prodan <[email protected]>
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‎soc/nxp/imxrt/imxrt7xx/CMakeLists.txt‎

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@@ -8,4 +8,6 @@ if(CONFIG_SOC_MIMXRT798S_CM33_CPU0 OR CONFIG_SOC_MIMXRT798S_CM33_CPU1)
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add_subdirectory(cm33)
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elseif(CONFIG_SOC_MIMXRT798S_HIFI4)
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add_subdirectory(hifi4)
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elseif(CONFIG_SOC_MIMXRT798S_HIFI1)
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add_subdirectory(hifi1)
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endif()

‎soc/nxp/imxrt/imxrt7xx/Kconfig‎

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@@ -48,6 +48,16 @@ config SOC_MIMXRT798S_HIFI4
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select GEN_ISR_TABLES
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select HAS_MCUX
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config SOC_MIMXRT798S_HIFI1
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select XTENSA
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select XTENSA_HAL if ("$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xcc" && "$(ZEPHYR_TOOLCHAIN_VARIANT)" != "xt-clang")
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select XTENSA_RESET_VECTOR
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select XTENSA_USE_CORE_CRT1
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select XTENSA_GEN_HANDLERS
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select XTENSA_SMALL_VECTOR_TABLE_ENTRY
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select GEN_ISR_TABLES
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select HAS_MCUX
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if SOC_SERIES_IMXRT7XX
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if NXP_IMXRT_BOOT_HEADER
@@ -65,5 +75,6 @@ config MCUX_CORE_SUFFIX
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default "_cm33_core0" if SOC_MIMXRT798S_CM33_CPU0
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default "_cm33_core1" if SOC_MIMXRT798S_CM33_CPU1
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default "_hifi4" if SOC_MIMXRT798S_HIFI4
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default "_hifi1" if SOC_MIMXRT798S_HIFI1
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endif # SOC_SERIES_IMXRT7XX

‎soc/nxp/imxrt/imxrt7xx/Kconfig.defconfig‎

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@@ -55,3 +55,25 @@ config NXP_IMXRT_BOOT_HEADER
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default n
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endif # SOC_MIMXRT798S_HIFI4
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if SOC_MIMXRT798S_HIFI1
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config SYS_CLOCK_HW_CYCLES_PER_SEC
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default $(dt_node_int_prop_int,/cpus/cpu@0,clock-frequency)
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config XTENSA_TIMER
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default y
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config GEN_IRQ_VECTOR_TABLE
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default n
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config NXP_IMXRT_BOOT_HEADER
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default n
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config XTENSA_CCOUNT_HZ
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default SYS_CLOCK_HW_CYCLES_PER_SEC
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config SYS_CLOCK_TICKS_PER_SEC
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default 1000
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endif # SOC_MIMXRT798S_HIFI1

‎soc/nxp/imxrt/imxrt7xx/Kconfig.soc‎

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@@ -29,9 +29,16 @@ config SOC_MIMXRT798S_HIFI4
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help
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NXP i.MXRT7xx HiFi4 DSP Core
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config SOC_MIMXRT798S_HIFI1
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bool
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select SOC_MIMXRT798S
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help
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NXP i.MXRT7xx HiFi1 DSP Core
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config SOC_TOOLCHAIN_NAME
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string
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default "nxp_rt700_hifi4" if SOC_MIMXRT798S_HIFI4
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default "nxp_rt700_hifi1" if SOC_MIMXRT798S_HIFI1
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config SOC_PART_NUMBER_MIMXRT798SGAWAR
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bool

‎soc/nxp/imxrt/imxrt7xx/hifi1/CMakeLists.txt‎

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#
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# Copyright 2024 NXP
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#
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# SPDX-License-Identifier: Apache-2.0
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#
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zephyr_include_directories(${CMAKE_CURRENT_SOURCE_DIR}/include)
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set(SOC_LINKER_SCRIPT ${CMAKE_CURRENT_SOURCE_DIR}/linker.ld CACHE INTERNAL "")

‎soc/nxp/imxrt/imxrt7xx/hifi1/include/dsp/cache.h‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __COMMON_DSP_CACHE_H__
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#define __COMMON_DSP_CACHE_H__
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#include <xtensa/hal.h>
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#endif

‎soc/nxp/imxrt/imxrt7xx/hifi1/include/dsp/io.h‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __INCLUDE_IO__
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#define __INCLUDE_IO__
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#include <stdint.h>
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#include <soc/memory.h>
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#include <zephyr/sys/sys_io.h>
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#include <zephyr/arch/common/sys_io.h>
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static inline uint32_t io_reg_read(uint32_t reg)
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{
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return sys_read32(reg);
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}
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static inline void io_reg_write(uint32_t reg, uint32_t val)
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{
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sys_write32(val, reg);
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}
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static inline void io_reg_update_bits(uint32_t reg, uint32_t mask, uint32_t value)
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{
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io_reg_write(reg, (io_reg_read(reg) & (~mask)) | (value & mask));
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}
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static inline uint16_t io_reg_read16(uint32_t reg)
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{
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return sys_read16(reg);
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}
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static inline void io_reg_write16(uint32_t reg, uint16_t val)
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{
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sys_write16(val, reg);
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}
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#endif

‎soc/nxp/imxrt/imxrt7xx/hifi1/include/soc.h‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#include <string.h>
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#include <errno.h>
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#include <zephyr/sys/sys_io.h>
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#include <dsp/cache.h>
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#ifndef __INC_IMXRT_SOC_H
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#define __INC_IMXRT_SOC_H
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/* Macros related to interrupt handling */
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#define XTENSA_IRQ_NUM_SHIFT 0
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#define XTENSA_IRQ_NUM_MASK 0xff
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/*
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* IRQs are mapped on levels. 2nd, 3rd and 4th level are left as 0x00.
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*
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* 1. Peripheral Register bit offset.
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*/
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#define XTENSA_IRQ_NUMBER(_irq) ((_irq >> XTENSA_IRQ_NUM_SHIFT) & XTENSA_IRQ_NUM_MASK)
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extern void z_soc_irq_enable(uint32_t irq);
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extern void z_soc_irq_disable(uint32_t irq);
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extern int z_soc_irq_is_enabled(unsigned int irq);
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#endif /* __INC_IMXRT_SOC_H */

‎soc/nxp/imxrt/imxrt7xx/hifi1/include/soc/memory.h‎

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/*
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* Copyright 2024 NXP
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*
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* SPDX-License-Identifier: Apache-2.0
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*/
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#ifndef __XTENSA_MEMORY_H__
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#define __XTENSA_MEMORY_H__
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#include <zephyr/autoconf.h>
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#define IRAM_RESERVE_HEADER_SPACE 0x400
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#define IRAM0_BASE 0x00580000
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#define IRAM0_SIZE 0x8000
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#define IRAM1_BASE 0x00680000
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#define IRAM1_SIZE 0x80000
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#define DRAM_BASE 0x20700000
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#define DRAM_SIZE 0x80000
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/* The reset vector address in IRAM and its size. */
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#define XCHAL_RESET_VECTOR0_PADDR_IRAM IRAM0_BASE
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#define MEM_RESET_TEXT_SIZE (0x2E0)
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#define MEM_RESET_LIT_SIZE (0x120)
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/* Base address of all interrupt vectors in IRAM. */
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#define XCHAL_VECBASE_RESET_PADDR_IRAM (IRAM0_BASE + IRAM_RESERVE_HEADER_SPACE)
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#define MEM_VECBASE_LIT_SIZE (0x178)
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/* Vector and literal sizes. */
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#define MEM_VECT_LIT_SIZE (0x4)
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#define MEM_VECT_TEXT_SIZE (0x1C)
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/* Addresses of the interrupt vectors. */
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#define XCHAL_INT_VECTOR_ADDR(x) (XCHAL_VECBASE_RESET_PADDR_IRAM + (x))
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#define XCHAL_INTLEVEL2_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x17C))
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#define XCHAL_INTLEVEL3_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x19C))
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#define XCHAL_INTLEVEL4_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1BC))
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#define XCHAL_INTLEVEL5_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1DC))
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#define XCHAL_KERNEL_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x1FC))
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#define XCHAL_USER_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x21C))
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#define XCHAL_DOUBLEEXC_VECTOR_PADDR_IRAM (XCHAL_INT_VECTOR_ADDR(0x23C))
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/* Location for the intList section which is later used to construct the
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* Interrupt Descriptor Table (IDT). This is a bogus address as this
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* section will be stripped off in the final image.
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*/
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#define IDT_BASE (IRAM0_BASE + IRAM0_SIZE)
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/* Size of the Interrupt Descriptor Table (IDT). */
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#define IDT_SIZE (0x2000)
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#endif

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